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DAC37J82 Datasheet(PDF) 5 Page - Texas Instruments |
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DAC37J82 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 122 page  DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014 – REVISED MAY 2014 Pin Functions (continued) PIN I/O DESCRIPTION NAME NUMBER CML SerDes interface lane 3 input, negative, expected to be AC coupled. It can be left open if RX3N M2 I not used. CML SerDes interface lane 4 input, positive, expected to be AC coupled. It can be left open if RX4P F1 I not used. CML SerDes interface lane 4 input, negative, expected to be AC coupled. It can be left open if RX4N E1 I not used. CML SerDes interface lane 5 input, positive, expected to be AC coupled. It can be left open if RX5P C1 I not used. CML SerDes interface lane 5 input, negative, expected to be AC coupled. It can be left open if RX5N D1 I not used. CML SerDes interface lane 6 input, positive, expected to be AC coupled. It can be left open if RX6P B1 I not used. CML SerDes interface lane 6 input, negative, expected to be AC coupled. It can be left open if RX6N A1 I not used. CML SerDes interface lane 7 input, positive, expected to be AC coupled. It can be left open if RX7P A3 I not used. CML SerDes interface lane 7 input, negative, expected to be AC coupled. It can be left open if RX7N A2 I not used. LVPECL SYSREF positive input with Vcm = 0.5V. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for JESD204B Subclass 1 deterministic latency and SYSREFP A7 I multiple DAC synchronization, which can be periodic or pulsed. If not used, it is self-biased with 100mV differential at Vcm = 0.5V. SYSREFN A6 I LVPECL SYSREF negative input with Vcm = 0.5V. (See the SYSREFP description) SCLK L9 I Serial interface clock. Internal pull-down. It can be left open if not used. Active low serial data enable, always an input to the DAC37J82/DAC38J82. Internal pull-up. It SDENB M9 I can be left open if not used. Serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-down. SDIO L10 I/O It can be left open if not used. Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface SDO M10 O mode (default). It can be left open if not used. Active high asynchronous hardware power-down input. Internal pull-down. It can be left open if SLEEP M8 I not used. SYNCBP B7 O Synchronization request to transmitter, LVDS positive output. It can be left open if not used. SYNCBN B6 O Synchronization request to transmitter, LVDS negative output. It can be left open if not used. Synchronization request to transmitter, CMOS output. Defaults to link 0, but can be SYNC_N_AB L6 O programmable for any link. It can be left open if not used. Synchronization request to transmitter, CMOS output. Defaults to link 1, but can be SYNC_N_CD L7 O programmable for any link. It can be left open if not used. TCLK K4 I JTAG test clock. It can be left open if not used. TDI L5 I JTAG test data in. It can be left open if not used. TDO M5 O JTAG test data out. It can be left open if not used. TMS L4 I JTAG test mode select. It can be left open if not used. JTAG test reset. Must be tied to GND to hold the JTAG state machine status reset if the JTAG TRSTB J3 I port is not used. To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS TXENABLE pin to high. Transmit enable active high input. Internal pull-down. To TXENABLE K5 I disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. It can be left open if not used. TESTMODE K3 O This pin is used for factory testing. Internal pull-down. It can be left open if not used. D10, E10, H10, VDDADAC33 I Analog supply voltage. (3.3V) J10, VDDAPLL18 B10, B9 I PLL analog supply voltage. (1.8V) VDDAREF18 C10, K10 I Analog reference supply voltage (1.8V) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DAC37J82 DAC38J82 |
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