Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
DLPC3430 Datasheet(PDF) 11 Page - Texas Instruments |
|
|
DLPC3430 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 41 page 11 DLP2010 www.ti.com DLPS046B – JULY 2014 – REVISED JULY 2016 Product Folder Links: DLP2010 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3. (2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3. (3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns. (4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. 6.7 Timing Requirements Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. MIN NOM MAX UNIT LPSDR tR Rise slew rate(1) (30% to 80%) × VDD, Figure 3 1 3 V/ns tV Fall slew rate(1) (70% to 20%) × VDD, Figure 3 1 3 V/ns tR Rise slew rate(2) (20% to 80%) × VDD, Figure 3 0.25 V/ns tF Fall slew rate(2) (80% to 20%) × VDD, Figure 3 0.25 V/ns tC Cycle time LS_CLK, Figure 2 7.7 8.3 ns tW(H) Pulse duration LS_CLK high 50% to 50% reference points,Figure 2 3.1 ns tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 2 3.1 ns tSU Setup time LS_WDATA valid before LS_CLK ↑, Figure 2 1.5 ns tH Hold time LS_WDATA valid after LS_CLK ↑, Figure 2 1.5 ns tWINDOW Window time(1)(3) Setup time + Hold time, Figure 2 3 ns tDERATING Window time derating(1)(3) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 5 0.35 ns SubLVDS tR Rise slew rate 20% to 80% reference points, Figure 4 0.7 1 V/ns tF Fall slew rate 80% to 20% reference points, Figure 4 0.7 1 V/ns tC Cycle time LS_CLK, Figure 6 1.61 1.67 ns tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6 0.71 ns tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6 0.71 ns tSU Setup time D(0:3) valid before DCLK ↑ or DCLK ↓, Figure 6 tH Hold time D(0:3) valid after DCLK ↑ or DCLK ↓, Figure 6 tWINDOW Window time Setup time + Hold time, Figure 6, Figure 7 0.3 ns tLVDS- ENABLE+REFGEN Power-up receiver(4) 2000 ns |
Número de pieza similar - DLPC3430 |
|
Descripción similar - DLPC3430 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |