SCAS842B – APRIL 2007 – REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to
generate a desired output frequency.
Assuming the requirement to generate an output frequency of 622.08 MHz, Table 1 shows that the desired
output frequency lies between 583.5 MHz and 680 MHz.
The feedback divider is set automatically with respect to the prescaler setting.
So this means that the device must be configured with:
VCO = VCO 1
Output divider = 1
Prescaler setting = 3
To determine the correct crystal frequency needed to get 622.08 MHz with these settings, substitute values into
The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz, as shown in Table 1) .
The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and
programmed via a single input pin to the device. The architecture enables only writing to the device from this
input pin. Reading the content of a register can be achieved by sending a read command on the input pin and
monitoring the output pins (LVDS or LVPECL). In cases where the output pins cannot be used to read the
content, the software controlling the interface must account for what is written to the EEPROM and when it is
programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies
that the EEPROM is holding the proper configuration.
The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave
programming sequence must be written to the device as described in the following section. During the EEPROM
programming phase, the device requires a stable VCC of 3 V to 3.6 V for secure writing of the EEPROM cells.
After each Write to WordX, the written data are latched, made effective, and offer look-ahead before the actual
data are stored into the EEPROM.
The following table summarizes all valid programming commands.
Enter Programming Mode (State 1
→ State 2); bits must be sent in the specified order with the specified timing.
Otherwise, a time-out occurs.
Enter Register Read Back Mode; bits must be sent in the specified order with the specified timing. Otherwise, a
000 xxxx xxxx
Write to Word0 (State 2)(1) (2) (3)
100 xxxx xxxx
Write to Word1 (State 2)(1) (2) (3)
010 xxxx xxxx
Write to Word2 (State 2)(1) (2) (3)
110 xxxx xxxx
Write to Word3 (State 2)(1) (2) (3)
Each rising edge causes a bit to be latched.
Between the bits, some longer time delays can occur, but this has no effect on the data.
A Write to WordX is expected to be 10 bits long. After the 10th bit, the respective word is latched and its effect can be observed as