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CDCDLP223PWR Datasheet(PDF) 1 Page - Texas Instruments

No. de pieza CDCDLP223PWR
Descripción Electrónicos  3.3 V Clock Synthesizer for DLP Systems
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

CDCDLP223PWR Datasheet(HTML) 1 Page - Texas Instruments

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FEATURES
XIN
1
20
XOUT
2
TSSOP 20
19
VSS
3
18
VDD
4
17
20MHZ
5
16
VSS
6
15
EN
7
14
IDO
8
13
SDATA
9
12
SCLK
10
11
IREF
VDD
100MHZ
100MHZ
VSS
VSS
300MHZ
300MHZ
VSS
VDD
TYPICAL APPLICATIONS
DESCRIPTION
CDCDLP223
SCAS836 – DECEMBER 2006
3.3 V Clock Synthesizer for DLP™ Systems
CDCDLP223 PIN ASSIGNMENTS
• High-Performance Clock Synthesizer
• Uses a 20 MHz Crystal Input to Generate
Multiple Output Frequencies
• Integrated Load Capacitance for 20 MHz
Oscillator Reducing System Cost
• All PLL Loop Filter Components are
Integrated
• Generates the Following Clocks:
REF CLK 20 MHz (Buffered)
XCG CLK 100 MHz With SSC
DMD CLK 200-400 MHz With Selectable
SSC
• Very Low Period Jitter Characteristic:
±100 ps at 20 MHz Output
±75 ps at 100 MHz and 200–400 MHz
Outputs
The 100 MHz HCLK output provides the reference
clock for the XDR Clock Generator (CDCD5704).
• Includes Spread-Spectrum Clocking (SSC),
Spread-spectrum clocking with 0.5% down spread,
With Down Spread for 100 MHz and Center
which reduces Electro Magnetic Interference (EMI),
Spread for 200–400 MHz
is
applied
in
the
default
configuration.
The
• HCLK Differential Outputs for the 100 MHz
spread-spectrum clocking (SSC) is turned on and off
and the 200–400 MHz Clock
via the serial control interface.
• Operates From Single 3.3-V Supply
The 300 MHz HCLK output provides a 200-400 MHz
• Packaged in TSSOP20
clock signal for the DMD Control Logic of the DLP™
Control ASIC. Frequency selection in 20 MHz steps
• Characterized for the Industrial Temperature
is
possible
via
the
serial
control
interface.
Range -40
°C to 85°C
Spread-spectrum clocking with
±1.0% or ±1.5%
• ESD Protection Exceeds JESD22
center spread is applied, which can be disabled via
• 2000-V Human-Body Model (A114-C) –
the serial control interface
MIL-STD-883, Method 3015
The CDCDLP223 features a fail safe start-up circuit,
which enables the PLLs only if a sufficient supply
voltage is applied and a stable oscillation is delivered
• Central Clock Generator for DLP™ Systems
from the crystal oscillator. After the crystal start-up
time and the PLL stabilization time, all outputs are
ready for use.
The CDCDLP223 is a PLL-based high performance
The CDCDLP223 works from a single 3.3-V supply
clock synthesizer that is optimized for use in DLP™
and is characterized for operation from –40
°C to
systems. It uses a 20 MHz crystal to generate the
85
°C.
fundamental frequency and derives the frequencies
for the 100 MHz HCLK and the 300 MHz HCLK
output.
Further,
the
CDCDLP223
generates
a
buffered copy of the 20 MHz Crystal Oscillator
Frequency at the 20 MHz output terminal.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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