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CDCFR83ADBQR Datasheet(PDF) 1 Page - Texas Instruments |
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CDCFR83ADBQR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 15 page www.ti.com FEATURES 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDDIR REFCLK VDDP GNDP GNDI PCLKM SYNCLKN GNDC VDDC VDDIPD STOPB PWRDNB S0 S1 VDDO GNDO CLK NC CLKB GNDO VDDO MULT0 MULT1 S2 DBQ PACKAGE (TOP VIEW) NC − No internal connection DESCRIPTION CDCFR83A SCAS812 – AUGUST 2005 DIRECT RAMBUS™ CLOCK GENERATOR • 533-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 1066-MHz Data Transfer Rate • Fail-Safe Power Up Initialization • Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock • Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications • Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ) • Packaged in a Shrink Small-Outline Package (DBQ) • Supports Frequency Multipliers: 4, 6, 8, 16/3 • No External Components Required for PLL • Supports Independent Channel Clocking • Spread Spectrum Clocking Tracking Capability to Reduce EMI • Designed for Use With TI's 133-MHz Clock Synthesizers CDC924 and CDC921 • Cycle-Cycle Jitter Is Less Than 40 ps at 533 MHz • Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement • Supports Industrial Temperature Range of –40 °C to 85°C The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DIRECT RAMBUS, Rambus are trademarks of Rambus Inc. PRODUCTION DATA information is current as of publication date. Copyright © 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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