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DS50PCI402 Datasheet(PDF) 20 Page - Texas Instruments |
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DS50PCI402 Datasheet(HTML) 20 Page - Texas Instruments |
20 / 38 page DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Table 10. SMBus Register Map (continued) 0x00 Reset 7:1 Reserved R/W 0x00 Set bits to 0. 0 Reset SMBus Reset 1: Reset registers to default value 0x01 PWDN Channels 7:0 PWDN CHx R/W 0x00 Power Down per Channel [7]: CHA_3 [6]: CHA_2 [5]: CHA_1 [4]: CHA_0 [3]: CHB_3 [2]: CHB_2 [1]: CHB_1 [0]: CHB_0 00'h = all channels enabled FF'h = all channels disabled 0x02 PWDN Control 7:1 Reserved R/W 0x00 Set bits to 0. 0 Override PWDN 0: Allow PWDN pin control 1: Block PWDN pin control 0x08 Pin Control Override 7:5 Reserved R/W 0x00 Set bits to 0. 4 Override IDLE 0: Allow IDLE pin control 1: Block IDLE pin control 3 Reserved Set bit to 0. 2 Override RATE 0: Allow RATE pin control 1: Block RATE pin control 1:0 Reserved Set bits to 0. 0x0E CH0 - CHB0 7:6 Reserved R/W 0x00 Set bits to 0. IDLE RATE Select 5 IDLE auto 0: Allow IDLE_sel control in Bit 4 1: Automatic IDLE detect 4 IDLE select 0: Output is ON (SD is disabled) 1: Output is muted (electrical idle) 3:2 Reserved Set bits to 0. 1 RATE auto 0: Allow RATE_sel control in Bit 0 1: Automatic RATE detect 0 RATE select 0: 2.5 Gbps 1: 5.0 Gbps 0x0F CH0 - CHB0 7:6 Reserved R/W 0x20 Set bits to 0. EQ Control 5:0 CH0 IB0 EQ IB0 EQ Control - total of 24 levels (3 gain stages with 8 settings) [5]: Enable EQ [4:3]: Gain Stage Control [2:0]: Boost Level Control Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex Value FF = 100000 = 20'h = Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h F0 = 110010 = 32'h 10 = 111001 = 39'h F1 = 110101 = 35'h 01 = 110111 = 37'h 0F = 111011 = 3B'h 1F = 111101 = 3D'h 0x10 CH0 - CHB0 7 Reserved R/W 0x03 Set bit to 0. VOD Control 5:0 CH0 OB0 VOD OB0 VOD Control 03'h = 600 mV (Default) 07'h = 800 mV 0F'h = 1000 mV 1F'h = 1200 mV 20 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 |
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