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DS50PCI402 Datasheet(PDF) 26 Page - Texas Instruments |
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DS50PCI402 Datasheet(HTML) 26 Page - Texas Instruments |
26 / 38 page DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Table 10. SMBus Register Map (continued) 0x35 CH5 - CHA1 7:0 CH5 OA1 DEM R/W 0x03 OA1 DEM Control DE Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 11101000 = E8'h = −3.5 dB 11 = 10001000 = 88'h = −6.0 dB 0F = 10010000 = 90'h = −9.0 dB 1F = 10100000 = A0'h = −12.0 dB F0 = 10010000 = 90'h = −9.0 dB F1 = 10100000 = A0'h = −12.0 dB FF = 11000000 = C0'h = Reserved 0x36 CH5 - CHA1 7:4 Reserved R/W 0x00 Set bits to 0. IDLE Threshold 3:0 IDLE threshold De-assert = [3:2], assert = [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x39 CH6 - CHA2 7:6 Reserved R/W 0x00 Set bits to 0. IDLE RATE Select 5 IDLE auto 0: Allow IDLE_sel control in Bit 4 1: Automatic IDLE detect 4 IDLE select 0: Output is ON (SD is disabled) 1: Output is muted (electrical idle) 3:2 Reserved Set bits to 0. 1 RATE auto 0: Allow RATE_sel control in Bit 0 1: Automatic RATE detect 0 RATE select 0: 2.5 Gbps 1: 5.0 Gbps 0x3A CH6 - CHA2 7:6 Reserved R/W 0x20 Set bits to 0. EQ Control 5:0 CH6 IA2 EQ IA2 EQ Control - total of 24 levels (3 gain stages with 8 settings) [5]: Enable EQ [4:3]: Gain Stage Control [2:0]: Boost Level Control Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex Value FF = 100000 = 20'h = Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h F0 = 110010 = 32'h 10 = 111001 = 39'h F1 = 110101 = 35'h 01 = 110111 = 37'h 0F = 111011 = 3B'h 1F = 111101 = 3D'h 0x3B CH6 - CHA2 7 Reserved R/W 0x03 Set bit to 0. VOD Control 5:0 CH6 OA2 VOD OA2 VOD Control 03'h = 600 mV (Default) 07'h = 800 mV 0F'h = 1000 mV 1F'h = 1200 mV 26 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 |
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