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DS50PCI402 Datasheet(PDF) 6 Page - Texas Instruments |
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DS50PCI402 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 38 page DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS50PCI402 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen 2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI402 operates in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1). Pin Control Mode: When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically increased per the De-Emphasis table below for improved performance over lossy media. The receiver detect pins RXDETA/B provide manual control for input termination (50 Ω or >50KΩ). Rate optimization is also pin controllable, with pin selections for 2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle detect threshold is also programmable via an optional external resistor on the SD_TH pin. SMBUS Mode: When in SMBus mode the equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by sides as in the pin mode case. Upon assertion of ENSMB the RATE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low. On powerup and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted while ENSMB is high, the registers retain their current state. Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus registers. Each input has a total of 24 possible equalization settings. The tables show a typical gain for each gain stage (GST[1:0]) and boost level (BST[2:0]) combination. When using SMBus mode, the Equalization and De- Emphasis levels are set using registers. Table 2. Equalization Settings with GST=1 for Pins or SMBus Registers EQ Setting EQ Gain (dB) EQ1( EQ0( Suggested Use GST[1 BST[2: 1.25 GHz 2.5 GHz 1) 1) :0] 0] F F 00 000 0 0 Bypass - Default Setting 01 000 1.6 3.2 01 001 2.1 4.2 1 1 01 010 2.6 5.0 8" FR4 (6-mil trace) or < 1m (28 AWG) PCIe cable 01 011 3.2 5.9 01 100 4.0 7.3 01 101 4.9 7.9 01 110 5.4 8.5 01 111 5.6 9.0 (1) F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers EQ Setting EQ Gain (dB) EQ1( EQ0( Suggested Use GST[1 BST[2: 1.25 GHz 2.5 GHz 1) 1) :0] 0] 0 0 10 000 3.8 7.6 14" FR4 (6-mil trace) or 1m (28 AWG) PCIe cable 10 001 5.1 9.9 F 0 10 010 6.4 11.6 20" FR4 (6-mil trace) or 5m (26 AWG) PCIe cable 10 011 7.6 13.5 10 100 9.5 16.1 F 1 10 101 11.3 17.5 40" FR4 (6-mil trace) or 9m (24 AWG) PCIe cable (1) F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low 6 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 |
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