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LM10502 Datasheet(PDF) 12 Page - Texas Instruments |
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LM10502 Datasheet(HTML) 12 Page - Texas Instruments |
12 / 35 page COMPARATOR SPI REGISTERS LDO SW1 BUCK1 EN FB_B1 GND_B1 SW_B1 VIN_B1 TSD VCOMP IRQ RESET STANDBY CONTROL LOGIC UVLO OVLO EN SW2 BUCK2 GND_B2 FB_B2 SW_B2 VIN_B2 LM10502 SNVS884B – AUGUST 2012 – REVISED MAY 2013 www.ti.com GENERAL DESCRIPTION LM10502 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and processors. It operates cooperatively and communicates with processors over an SPI interface with output Voltage programmability. The device incorporates two high-efficiency synchronous buck regulators and one LDO that deliver four output voltages from a single power source. The device also includes a SPI-programmable Comparator Block that provides an interrupt output signal. Figure 18. Internal Block Diagram of the LM10502 PMIC 12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM10502 |
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