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ADUM1100BR Datasheet(PDF) 5 Page - Analog Devices |
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ADUM1100BR Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page REV. E –5– ADuM1100 Parameter Symbol Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS (continued) Propagation Delay Skew tPSK2 (Equal Temperature, Supplies) 6, 8 5 V/3 V Operation 9 ns CL = 15 pF, CMOS Signal Levels 3 V/5 V Operation 12 ns CL = 15 pF, CMOS Signal Levels Output Rise/Fall Time (10% to 90%) tR, tf 3ns CL = 15 pF, CMOS Signal Levels Common-Mode Transient Immunity at Logic Low/High Output 8 |CML|, 25 35 kV/ µsV I = 0 or VDD1, VCM = 1000 V, |CMH|Transient Magnitude = 800 V Input Dynamic Power Dissipation Capacitance 10 CPD1 5 V/3 V Operation 35 pF 3 V/5 V Operation 47 pF Output Dynamic Power Dissipation Capacitance 10 CPD2 5 V/3 V Operation 8 pF 3 V/5 V Operation 14 pF NOTES 1All voltages are relative to their respective ground. 2Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by IDD2(L) = IDD2 + VDD2 × f × C L, where IDD2 is the unloaded output supply current, f is the input signal frequency, and CL is the output load capacitance. 3The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5t PHL is measured from the 50% level of the falling edge of the V I signal to the 50% level of the falling edge of the V O signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 6Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figures 3 to 7 for information on the impact of given input rise/fall times on these parameters. 7Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1 °C change in operating temperature. 8t PSK1 is the magnitude of the worst-case difference in t PHL and/or tPLH that will be measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that will be measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 9CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common-mode is slewed. 10The dynamic power dissipation capacitance is given by CPDi = (IDDi(100) – IDDi(Q))/(VDDi × f), where i = 1 or 2 and f is the input signal frequency. The supply current consumptions at a given frequency and output load are calculated as IDD1 = CPD1 × V DD1 × f + I DD1(Q); IDD2(L) = (CPD2 + CL) × V DD2 × f + I DD2(Q), where CL is the output load capacitance. Specifications subject to change without notice. PACKAGE CHARACTERISTICS Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-Output) 1 RI–O 10 12 Ω Capacitance (Input-Output) 1 CI–O 1pF f = 1 MHz Input Capacitance 2 CI 4.0 pF Input IC Junction-to-Case θ JCI 46 °C/W Thermocouple Located at Center Thermal Resistance Underside of Package Output IC Junction-to-Case θJCO 41 °C/W Thermal Resistance Package Power Dissipation PPD 240 mW NOTES 1Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together. 2Input capacitance is measured at Pin 2 (V I). |
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