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SN74ABT3612 Datasheet(PDF) 6 Page - Texas Instruments

No. de pieza SN74ABT3612
Descripción Electrónicos  CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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Fabricante Electrónico  TI1 [Texas Instruments]
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SN74ABT3612 Datasheet(HTML) 6 Page - Texas Instruments

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SN74ABT3612
64
× 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
PIN NAME
I/O
DESCRIPTION
MBF2
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
ODD/
EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked
when ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
PEFA
O
(port A)
Port-A parity error flag. When any byte applied to A0 – A35 fails parity, PEFA is low. Bytes are organized as
A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte serving as the parity bit.
The type of parity checked is determined by the state of ODD/EVEN.
The parity trees used to check the A0 – A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having W/RA low,
MBA high, and PGA high, PEFA is forced high regardless of the state of the A0 – A35 inputs.
PEFB
O
(port B)
Port-B parity error flag. When any byte applied to terminals B0 – B35 fails parity, PEFB is low. Bytes are organized
as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte serving as the parity bit.
The type of parity checked is determined by the state of ODD/EVEN.
The parity trees used to check the B0 – B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having W/RB low,
MBB high, and PGB high, PEFB is forced high regardless of the state of the B0 – B35 inputs.
PGA
I
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity
generated is selected by the state of ODD/EVEN. Bytes are organized as A0 – A8, A9 – A17, A18 – A26, and
A27 – A35. The generated parity bits are output in the most-significant bit of each byte.
PGB
I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity
generated is selected by the state of ODD/EVEN. Bytes are organized as B0 – B8, B9 – B17, B18 – B26, and
B27 – B35. The generated parity bits are output in the most-significant bit of each byte.
RST
I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must
occur while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low.
The low-to-high transition of RST latches the status of FS1 and FS0 to select almost-full flag and almost-empty
flag offset.
W/RA
I
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high.
W/RB
I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is high.
detailed description
reset
The SN74ABT3612 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the empty
flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high. A reset
also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high transitions
of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after power
up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.


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