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LM3559 Datasheet(PDF) 6 Page - Texas Instruments |
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LM3559 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 50 page  6 LM3559 SNVS624B – JUNE 2011 – REVISED JUNE 2016 www.ti.com Product Folder Links: LM3559 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise specified, VIN = 3.6 V, VHWEN = VIN, TA = 25°C. (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ƒSW Switching frequency 2.7 V ≤ VIN ≤ 5.5 V 2 MHz 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 1.8 2.2 IQ Quiescent supply current Device not switching, VOUT = 3V 650 µA Device switching, VOUT = 4.5V 1.55 mA Indicate mode, Indicator Register bits [2:0] = 111 VLEDI/NTC = 2 V 590 µA Indicate mode, Indicator Register bits [2:0] = 111 VLEDI/NTC = 2 V, –40°C ≤ TA ≤ 85°C 750 ISHDN Shutdown supply current 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C HWEN = GND 1 µA ISTBY Standby supply current 2.7 V ≤ VIN ≤ 5.5 V HWEN = VIN, Enable Register bits [1:0] = 00 1.25 µA 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 2.4 VIN_TH VIN monitor threshold VIN Monitor Register = 0x01 2.9 V VIN Monitor Register = 0x01, –40°C ≤ TA ≤ 85°C 2.85 2.95 VIN_FLASH_TH VIN flash monitor threshold VIN Monitor Register = 0x08 2.9 V VIN Monitor Register = 0x08, –40°C ≤ TA ≤ 85°C 2.85 2.95 tTX Flash-to-torch LED current settling time TX_ Low to High ILED1 + ILED2 = 1.8A to 112.5mA 20 µs tD Time from when ILED hits target until VLED data is available ADC Delay Register bit [5] = 1 16 µs ADC Delay Register bit [5] = 0 ADC Delay Register bits [4:0] = 0000 250 VF_ADC ADC threshold VLED Monitor Register bits [3:0] = 1111 4.6 V VLED Monitor Register bits [3:0] = 1111 –40°C ≤ TA ≤ 85°C 4.4 4.8 HWEN, STROBE, TX1/TORCH/GPIO1, TX2/INT/GPIO2 VOLTAGE SPECIFICATIONS VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 0 0.4 V VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 1.2 VIN V RPD Internal pulldown resistance on TX1, TX2, STROBE 300 k Ω I2C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA) VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 0 0.4 V VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V 1.3 VIN V VOL Output logic low (SDA) ILOAD = 3 mA 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 0.4 V (1) Specified by design, not production tested. 6.6 I 2C Timing Requirements (SCL, SDA) See (1) MIN NOM MAX UNIT 1/t1 SCL(clock frequency) 400 kHz t2 Data in setup time to SCL high 100 ns t3 Data out stable after SCL low 0 ns t4 SDA low setup time to SCL low (start) 100 ns t5 SDA high hold time after SCL high (stop) 100 ns |
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