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SN74AHCT240PW Datasheet(PDF) 10 Page - Texas Instruments

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No. de pieza SN74AHCT240PW
Descripción Electrónicos  SNx4AHCT240 Octal Buffers/Drivers With 3-State Outputs
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Fabricante Electrónico  TI1 [Texas Instruments]
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SN74AHCT240PW Datasheet(HTML) 10 Page - Texas Instruments

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Vcc
Unused Input
Input
Output
Input
Unused Input
Output
10
SN54AHCT240, SN74AHCT240
SCLS252M – OCTOBER 1995 – REVISED APRIL 2016
www.ti.com
Product Folder Links: SN54AHCT240 SN74AHCT240
Submit Documentation Feedback
Copyright © 1995–2016, Texas Instruments Incorporated
Typical Application (continued)
10.2.3 Application Curves
Figure 4. Application Scope Capture
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1
μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1
μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Such examples are when only two inputs of a triple-input AND gate are used, or
only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states.
Specified in Figure 5 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Figure 5. Layout Diagram


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