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SN74ALVCH162820DGGR Datasheet(PDF) 1 Page - Texas Instruments

No. de pieza SN74ALVCH162820DGGR
Descripción Electrónicos  3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ALVCH162820DGGR Datasheet(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
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1OE
1Q1
1Q2
GND
2Q1
2Q2
VCC
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
VCC
9Q1
9Q2
GND
10Q1
10Q2
2OE
CLK
D1
NC
GND
D2
NC
VCC
D3
NC
D4
GND
NC
D5
NC
D6
NC
D7
GND
NC
D8
NC
VCC
D9
NC
GND
D10
NC
NC
DGG OR DL PACKAGE
(TOP VIEW)
NC − No internal connection
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
SN74ALVCH162820
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES012H – JULY 1995 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-
Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
This 10-bit flip-flop is designed for 1.65-V to 3.6-V
VCC operation.
The SN74ALVCH162820 flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the
clock (CLK) input, the device provides true data at the
Q outputs.
A buffered output-enable (OE) input can be used to
place the ten outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load
nor
drive
the
bus
lines
significantly.
The
high-impedance state and increased drive provide the
capability to drive bus lines without need for interface
or pullup components.
while the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-
Ω resistors to reduce overshoot and
undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162820 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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