TPS70845, TPS70848, TPS70851, TPS70858, TPS70802

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

SLVS301B – JUNE 2000 – REVISED OCTOBER 2002

5

POST OFFICE BOX 655303

RESET timing diagram

VIN1

VUVLO

VUVLO

t

t

t

MR Input

RESET Output

120 ms

Delay

120 ms

Delay

NOTE A: VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for

semiconductor symbology.

VRES

Output

Undefined

Output

Undefined

VRES

PG1 timing diagram

VPG1

t

t

t

PG1 Output

VIT+

(see Note B)

VIN1

VOUT1

VPG1

VIT –

(see Note B)

VUVLO

VUVLO

PG1

NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

B. VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.

Threshold

Voltage

Output

Undefined

Output

Undefined