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TPS70845PWP Datasheet(PDF) 2 Page - Texas Instruments

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No. de pieza TPS70845PWP
Descripción Electrónicos  DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
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Fabricante Electrónico  TI [Texas Instruments]
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TPS70845PWP Datasheet(HTML) 2 Page - Texas Instruments

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TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices
have extremely low noise output performance without using any added filter bypass capacitors and are
designed to have a fast transient response and be stable with 10
µF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.
Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow
the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV
on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is
a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
230
µA over the full range of output current and full range of temperature). This LDO family also features a sleep
mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When
a high signal is applied to both EN1 and EN2, both regulators are in sleep mode, thereby reducing the input
current to 2
µA at TJ = 25°C.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET,
POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions
at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by
regulator 2.
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event
of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the
logic high state, RESET goes to a high-impedance state after 120 ms delay. To monitor VOUT1, the PG1 output
pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR.
The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until
VIN1 reaches 2.5V.
AVAILABLE OPTIONS
TJ
REGULATOR 1
VO (V)
REGULATOR 2
VO (V)
TSSOP
(PWP)
3.3 V
1.2 V
TPS70845PWP
3.3 V
1.5 V
TPS70848PWP
– 40
°Cto125°C
3.3 V
1.8 V
TPS70851PWP
– 40
°C to 125°C
3.3 V
2.5 V
TPS70858PWP
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70802PWP
NOTE: The TPS70802 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70802PWPR).


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