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LM8328 Datasheet(PDF) 8 Page - Texas Instruments

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No. de pieza LM8328
Descripción Electrónicos  LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
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LM8328
SNLS328A – AUGUST 2011 – REVISED MARCH 2013
www.ti.com
In the timing diagram shown in Figure 5 the LM8328 resides in sleep mode. Since the LM8328 device can’t
acknowledge the slave address the host must generate a STOP condition followed by a second START
condition.
On the second attempt the slave address is being acknowledged from the LM8328 device because it is in
active mode now.
The host can send different WRITE and/or READ commands subsequently after each other.
The host must finally free the bus by generating a STOP condition.
ACCESS.Bus Communication Flow
The LM8328 will only be driven in slave mode. The maximum communication speed supported is Fast Mode
(FS) which is 400 kHz. The device can be heavily loaded as it is processing different kind of events caused from
the human interface and the host device. In such cases the LM8328 may temporarily be unable to accept new
commands and data sent from the host device.
NOTE
“It is a legitimate measure of the slave device to hold SCL line low in such cases in order
to force the master device into a waiting state. It is therefore the obligation of the host
device to detect such cases. Typically there is a control bit set in the master device
indicating the Busy status of the bus. As soon as the SCL line is released the host can
continue sending commands and data.”
Further Remarks:
In systems with multiple masters it is recommended to separate commands with Repeat START conditions
rather than sending a STOP - and another START - condition to communicate with the LM8328 device.
Delays enforced by the LM8328 during very busy phases of operation should typically not exceed a duration
of 100 usec.
Normally the LM8328 will clock stretch after the acknowledge bit Is transmitted; however, there are some
conditions where the LM8328 will clock stretch between the SDA Start bit and the first rising edge of SCL.
Auto Increment
In order to improve multi-byte register access, the LM8328 supports the auto increment of the address pointer.
A typical protocol access sequence to the LM8328 starts with the I2C-compatible ACCESS.bus address, followed
by REG, the register to access (see Figure 4). After a REPEATED START condition the host reads/writes a data
byte from/to this address location. If more than one byte is transmitted, the LM8328 automatically increments the
address pointer for each data byte by 1. The address pointer keeps the status until the STOP condition is
received.
The LM8328 always uses auto increments unless otherwise noted.
Please refer to Table 2 and Table 3 for the typical ACCESS.bus flow of reading and writing multiple data bytes.
Reserved Registers and Bits
The LM8328 includes reserved registers for future implementation options. Please use value 0 on a write to all
reserved register bits.
Global Call Reset
The LM8328 supports the Global Call Reset as defined in the I2C Specification, which can be used by the host to
reset all devices connected to interface. The Global call reset is a single byte ACCESS.bus/I2C write of data byte
0x06 to slave address 0x00.
The Global Call Reset changes the I2C-compatible ACCESS.bus Slave address of the LM8328 back to its default
value of 0x88.
8
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