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LMZ31520RLGT Datasheet(PDF) 4 Page - Texas Instruments |
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LMZ31520RLGT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 30 page LMZ31520 SLVSBM9B – OCTOBER 2013 – REVISED DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C, VIN = 12 V, VOUT = 1.8 V, IOUT = 20A CIN = 2x 22 µF ceramic & 330 µF bulk, COUT = 4x 100 µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOUT Output current 0 20 A VIN Input bias voltage range Over IOUT range 4.5 14.5 V PVIN Input switching voltage range Over IOUT range 3.0(1) 14.5 V VIN Increasing 4.0 4.2 4.33 V UVLO VIN Undervoltage lockout Hysteresis 0.25 VOUT(adj) Output voltage adjust range Over IOUT range 0.6 3.6 V Set-point voltage tolerance IOUT = 20 A, FCCM mode ±1.0% (2) Temperature variation -40°C ≤ TA ≤ +85°C ±0.25% VOUT Load regulation Over IOUT range +0.3% Total output voltage variation Includes set-point, load, and temperature variation ±1.8% (2) PVIN ±10% ±0.1% Line regulation Over PVIN range ±0.5% VOUT = 3.3 V, fSW = 500kHz 94 VOUT = 1.8 V, fSW = 500kHz 92 PVIN = VIN = 12 V VOUT = 1.2 V, fSW = 500kHz 88 % IO = 15 A VOUT = 0.9 V, fSW = 500kHz 86 VOUT = 0.6 V, fSW = 500kHz 82 η Efficiency PVIN = VIN = 5 V VOUT = 3.3 V, fSW = 500kHz 96 IO = 15 A VOUT = 1.8 V, fSW = 500kHz 94 VOUT = 1.2 V, fSW = 500kHz 91 % VOUT = 0.9 V, fSW = 500kHz 88 VOUT = 0.6 V, fSW = 500kHz 85 Output voltage ripple 20 MHz bandwith 1% VOUT ILIM Current limit threshold 30 A Recovery time 25 µs 2.5 A/µs load step from 25 to 75% Transient response IOUT(max) VOUT over/undershoot 25 mV Inhibit High Voltage 1.8 Open(3) V VINH Inhibit Control Inhibit Low Voltage -0.3 0.6 V VIN = 5 V 0.5 0.7 mA IIN(stby) VIN standby current INH pin to AGND VIN = 12 V 1.2 1.5 mA Good 95 VOUT rising Fault 115 PWRGD Thresholds % Power Good Fault 90 VOUT falling Good 110 PWRGD Low Voltage I(PWRGD) = 2 mA 0.2 0.3 V fSW Switching frequency FREQ_SEL pin OPEN, IOUT = 10 A 470 520 570 kHz 66 k Ω resistor between FREQ_SEL pin and PGND 300 kHz fSEL Frequency Select(4) FREQ_SEL pin connected to V5V (pin 61) 850 kHz Thermal shutdown 145 °C Thermal Shutdown Thermal shutdown hysteresis 10 °C Ceramic 44 (5) 94 CIN External input capacitance µF Non-ceramic 330 (1) The minimum PVIN voltage is 3.0V or (VOUT+ 1.1V), whichever is greater. See VIN and PVIN Input Voltage for more details. (2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor. (3) This pin has an internal pull-up to approximately 0.4 x VIN. If this pin is left open circuit, the device operates when a valid input voltage is applied. A small, low-leakage (<300nA) MOSFET is recommended for control. (4) See the Frequency Select section for more information on selecting the frequency. (5) A minimum of 44 µF (2x 22 µF) of external ceramic capacitance is required across the input (PVIN/VIN and PGND connected) for proper operation. Locate the capacitor close to the device. See Table 3 for more details. When operating with split VIN and PVIN rails, place 4.7 µF of ceramic capacitance directly at the VIN pin to PGND. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31520 |
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