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UC1848 Datasheet(PDF) 7 Page - Texas Instruments |
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UC1848 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 13 page 7 UC1848 UC2848 UC3848 If the system is not sensitive to short circuit requirements, Figure 5 shows the simplest method of downslope gener- ation: a single resistor (ROFF = 40k) from IOFF to VREF. The discharge current is then 100 µA. The disadvantage to this approach is that the synthesizer continues to gen- erate a down slope when the switch is off even during short circuit conditions. Actual inductor down slope is closer to zero during a short circuit. The penalty is that the average current is understated by an amount approxi- mately equal to the nominal inductor ripple current. Out- put short circuit is therefore higher than the designed maximum output current. A third method of generating IOFF is to add a second winding to the output inductor core (Fig. 6). When the power switch is off and inductor current flows in the free wheeling diode, the voltage across the inductor is equal to the output voltage plus the diode drop. This voltage is then transformed by the second winding to the primary side of the converter. The advantages to this approach are its inherent accuracy and bandwidth. Winding the second coil on the output inductor core while maintaining the required isolation makes this a more costly solution. In the example, ROFF = VO / 100µA. The 4 • ROFF re- sistor is added to compensate the one volt input level of the IOFF pin. Without this compensation, a minor current foldback behavior will be observed. APPLICATION INFORMATION (cont.) UDG-93010 UDG-93011 UDG-93009 |
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