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TDA2SG Datasheet(PDF) 1 Page - Texas Instruments |
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TDA2SG Datasheet(HTML) 1 Page - Texas Instruments |
1 / 426 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TDA2SX, TDA2SG TDA2HG, TDA2HV, TDA2LF SPRS951A – DECEMBER 2015 – REVISED APRIL 2016 TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0 1 Device Overview 1 1.1 Features 1 • Architecture Designed for ADAS Applications • Video, Image, and Graphics Processing Support – Full-HD Video (1920 × 1080p, 60 fps) – Multiple Video Input and Video Output • ARM® Dual Cortex®-A15 Microprocessor Subsystem • Up to Two C66x™ Floating-Point VLIW DSP – Fully Object-Code Compatible With C67x™ and C64x+™ – Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle • Up to 2.5MB of On-Chip L3 RAM • Level 3 (L3) and Level 4 (L4) Interconnects • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules – Supports up to DDR2-800 and DDR3-1066 – Up to 2GB Supported per EMIF • Two ARM® Dual Cortex®-M4 Image Processing Units (IPUs) • Vision AccelerationPac – Up to Four Embedded Vision Engines (EVEs) • IVA-HD Subsystem • Display Subsystem – Display Controller With DMA Engine and up to Three Pipelines – HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant • 2D-Graphics Accelerator (BB2D) Subsystem – Vivante™ GC320 Core • Video Processing Engine (VPE) • Dual-Core PowerVR® SGX544™ 3D GPU • Three Video Input Port (VIP) Modules – Support for up to 10 Multiplexed Input Ports • General-Purpose Memory Controller (GPMC) • Enhanced Direct Memory Access (EDMA) Controller • 2-Port Gigabit Ethernet (GMAC) • Dual Controller Area Network (DCAN) Modules – CAN 2.0B Protocol • PCI-Express® 2.0 Port With Integrated PHY – One 2-lane Gen2-Compliant Port – or Two 1-lane Gen2-Compliant Ports • Sixteen 32-Bit General-Purpose Timers • 32-Bit MPU Watchdog Timer • Ten Configurable UART/IrDA/CIR Modules • Four Multichannel Serial Peripheral Interfaces (MCSPIs) • Quad SPI Interface • Five Inter-Integrated Circuit (I2C) Ports • SATA Interface • Multichannel Audio Serial Port (MCASP) • SuperSpeed USB 3.0 Dual-Role Device • Up to 247 General-Purpose I/O (GPIO) Pins • Real-Time Clock Subsystem (RTCSS) • Devise security features – Hardware Crypto accelerators and DMA – Firewalls – JTAG lock – Secure keys – Secure ROM and boot • Power, Reset, and Clock Management • On-Chip Debug With CTools Technology • Automotive AEC-Q100 Qualified • 28-nm CMOS Technology • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC) |
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