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UC1843A Datasheet(Hoja de datos) 4 Page - Texas Instruments

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No. de Pieza. UC1843A
Descripción  Current-Mode PWM Controller
Descarga  45 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 4 page
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4
UC1842A, UC1843A, UC1844A, UC1845A
UC2842A, UC2843A, UC2844A, UC2845A
UC3842A, UC3843A, UC3844A, UC3845A
SLUS224E – SEPTEMBER 1994 – REVISED JULY 2016
www.ti.com
Product Folder Links: UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A
UC3843A UC3844A UC3845A
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Copyright © 1994–2016, Texas Instruments Incorporated
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CDIP (8),
PDIP (8),
SOIC (8)
LCCC (20),
PLCC (20)
SOIC (14)
SOIC (16)
COMP
1
2
1
3
O
Outputs the low impedance 1-MHz internal error amplifier that is also
the input to the peak current limit or PWM comparator, with an open-
loop gain (AVOL) of 80 dB. This pin is capable of sinking a maximum
of 6 mA and is not internally current limited.
FB
2
5
3
4
I
Input to the error amplifier that can be used to control the power
converter voltage-feedback loop for stability.
GND
5
13
9
11
This is the controller signal ground.
ISENSE
3
7
5
5
I
Input to the peak current limit, PWM comparator of the UCx84xA
controllers. When used in conjunction with a current sense resistor,
the error amplifier output voltage controls the power systems cycle-
by-cycle peak current limit. The maximum peak current sense signal
is internally clamped to 1 V. See Functional Block Diagram.
OUTPUT
6
15
10
12
O
Output of 1-A totem pole gate driver. This pin can sink and source
up to 1 A of gate driver current. A gate driver resistor must be used
to limit the gate driver current.
PGND
12
8
10
Power ground and the gate driver return. For devices that have this
pin, star grounding techniques can be used to redirect the gate
driver current away from the signal ground pin (GND). This
technique can reduce PWM controller instabilities caused by gate
driver return current.
RT/CT
4
10
7
6
I
Input to the internal oscillator that is programmed with an external
timing resistor (RT) and timing capacitor (CT). See Oscillator for
information on properly selecting these timing components. TI
recommends using capacitance values from 470 pF to 4.7 nF. TI
also recommends that the timing resistor values chosen be from
5 kΩ to 100 kΩ.
VC
17
11
I
Bias input to the gate driver. For PWM controllers that do not have
this pin, the gate driver is biased from the VCC pin. This pin must
have a biasing capacitor that is at least 10 times greater than the
gate capacitance of the main switching FET used in the design.
VCC
7
18
12
13, 14
I
Bias input to the gate driver. This pin must have a biasing capacitor
that is at least 10 times greater than the gate capacitance of the
main switching FET used in the design.
VREF
8
20
14
15
O
Reference voltage output of the PWM controller. This pin must
supply no more than 10 mA under normal operation. This output is
short-circuit protected at roughly 100 mA. This reference is also used
for internal comparators and needs a high frequency bypass
capacitor of 1 µF. The VCC capacitor also must be at least 10 times
greater than the capacitor on the VREF pin.
NC
1, 3, 4, 6, 8,
9, 11, 14,
16, 19
2, 4, 6, 13
1, 2, 7, 8,
9, 16
No connection




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