UCC27221

UCC27222

SLUS486B − AUGUST 2001 − REVISED JULY 2003

7

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APPLICATION INFORMATION

A typical application circuit for systems with 8.5-V to 20-V input is shown in Figure 3.

CIN

C2

R1

C1

PWM

Input

D1

GND

VIN

VHI

G1

SW

SWS

PVLO

N/C

VDD

VLO

G2S

G2

PGND

AGND

IN

N/C

UCC27222

L1

Cout

Q1

Q2

V OUT

GND

Figure 3. System Application: 8.5-V to 20-V Input

selection of VHI series resistor R1 (dV/dt Considerations):

The series resistor R1 may be needed to slowdown the turn-on of the main forward switch to limit the dV/dt which

can inadvertently turn on the synchronous rectifier switch. In nominal 12-V input designs, a R1 value of 4-

Ω to

10-

Ω can be used depending on the type of MOSFET used and the high-side/low-side MOSFET ratio. In 5-V

or lower input applications however, R1 is not needed.

When the drain-source voltage of a MOSFET quickly rises, inadvertent dV/dt induced turn-on of the device is

possible. This can especially be a problem for input voltages of 12 V or greater. As Q1 rapidly turns on, the

drain-to-source voltage of Q2 rises sharply, resulting in a dV/dt voltage spike appearing on the gate signal of

Q2. If the dV/dt induced voltage spike were to exceed the given threshold voltage, the MOSFET may briefly

turn on when it should otherwise be commanded off. Obviously this undesired event would have a negative

impact on overall efficiency.

Minimizing the dV/dt effect on Q2 can be accomplished by proper MOSFET selection and careful layout

techniques. The details of how to select a MOSFET to minimize dV/dt susceptibility are outlined in SEM−1400,

Topic 2, Appendix A, Section A5. Secondly, the switch node connecting Q1, Q2 and L1 should be laid out as

tight as possible, minimizing any parasitic inductance, which might worsen the dV/dt problem.

If the dV/dt induced voltage spike is still present on the gate Q2, a 4W to 10W value of R1 is recommended to

minimize the possibility of inadvertently turning on Q2. The addition of R1 slows the turn-on of Q1, limiting the

dV/dt rate appearing on the drain-to-source of Q2. Slowing down the turn-on of Q1 will result in slightly higher

switching loss for that device only, but the efficiency gained by preventing dV/dt turn-on of Q2 will far outweigh

the negligible effect of adding R1.

When Q2 is optimally selected for dV/dt robustness and careful attention is paid to the PCB layout of the switch

node, R1 may not be needed at all, and can therefore be replaced with a 0-

Ω jumper to maintain high efficiency.

The goal of the designer should not be to completely eliminate the dV/dt turn-on spike but to assure that the

maximum amplitude is less than the MOSFET gate-to-source turn-on threshold voltage under all operating

conditions.

UCC27221

Not Recommended For New Designs