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TMP461 Datasheet(PDF) 6 Page - Texas Instruments |
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TMP461 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 35 page SCL SDA t (LOW) t R t F t (HDSTA) t (HDSTA) t (HDDAT) t (BUF) t (SUDAT) t (HIGH) t (SUSTA) t (SUSTO) P S S P 6 TMP461 SBOS722B – JUNE 2015 – REVISED AUGUST 2016 www.ti.com Product Folder Links: TMP461 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 7.6 Two-Wire Timing Requirements At –40°C to 125°C and V+ = 1.7 V to 3.6 V, unless otherwise noted. FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX f(SCL) SCL operating frequency 0.001 0.4 0.001 2.17 MHz t(BUF) Bus free time between stop and start condition 1300 160 ns t(HDSTA) Hold time after repeated start condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) Repeated start condition setup time 600 160 ns t(SUSTO) Stop condition setup time 600 160 ns t(HDDAT) Data hold time 0 900 0 150 ns t(SUDAT) Data setup time 100 40 ns t(LOW) SCL clock low period 1300 320 ns t(HIGH) SCL clock high period 600 60 ns tF – SDA Data fall time 300 130 ns tF, tR – SCL Clock fall and rise time 300 40 ns tR Rise time for SCL ≤ 100 kHz 1000 ns Figure 1. Two-Wire Timing Diagram |
Número de pieza similar - TMP461_16 |
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Descripción similar - TMP461_16 |
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