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UCD90240 Datasheet(PDF) 39 Page - Texas Instruments

No. de pieza UCD90240
Descripción Electrónicos  UCD90240 24-Rail PMBus Power Sequencer and System Manager
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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UCD90240 Datasheet(HTML) 39 Page - Texas Instruments

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UCD90240
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SLVSCW0 – FEBRUARY 2015
There may be situations where it is required to update the device configuration in an operating system. The
PMBus command method can be used to update thresholds, timeout periods, dependencies, and so forth, while
the system is operating. Because the new configuration is written into RAM, it will take effect immediately.
However, pin-function-related configurations (for example, change of rails, change of GPI/GPO functions, and so
forth) may not work correctly until a device reset. This may be a problem in an operating system. For example,
undesired GPI/GPO/System Reset pin states may disable rails that provide power to the UCD90240, and thus
terminate the programming process before it is completed. The data flash image method can overcome this
problem by directly writing new configuration into the data flash. This allows a full configuration while the system
is operating. It is not required to reset the device immediately but the UCD90240 will continue to operate based
on previous configuration until a device reset.
The JTAG port is compatible with IEEE Standard 1149.1-1990, Test-Access Port and Boundary Scan
Architecture specification. UCD90240 supports boundary scan. Configuration programming via JTAG is not
supported on this device.
7.3.23 Internal Fault Management
The UCD90240 verifies the firmware program checksum at each power up. If the checksum does not match, the
device will reset. If the device keeps resetting, the SYNC_CLK pin will output repeated pulses with ~250-ms
pulse width that can be observed externally.
The configuration data checksum verification is also performed at power up. If the checksum does not match, the
device will wipe out all the configuration data. The PMBALERT# pin is asserted and a flag is set in the status
register.
A fault-log checksum verification in EEPROM is also performed at power up. Each log entry has a checksum.
The corrupted log entry will be discarded.
There is an internal firmware watchdog timer. If it times out, the device resets so that if the firmware program is
corrupted, the device goes back to a known state. This is a normal device reset, so all of the I/O pins are held in
high-impedance while the device is in reset. Checks are also done on each parameter that is passed, to make
sure it falls within the acceptable range.
Copyright © 2015, Texas Instruments Incorporated
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