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UCD90240 Datasheet(Hoja de datos) 43 Page - Texas Instruments

No. de Pieza. UCD90240
Descripción  UCD90240 24-Rail PMBus Power Sequencer and System Manager
Descarga  49 Pages
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Fabricante  TI1 [Texas Instruments]
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 43 page
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9 Power Supply Recommendations
UCD90240 should be powered by a 3.3-V power supply.
If internal reference is used, V33A is used as ADC reference and is assumed to be exactly 3.3 V. Any input
voltage deviation from 3.3 V will introduce an error to ADC reference and thus ADC results. Therefore, the 3.3-V
power supply must be tightly regulated and with very small voltage fluctuation (including voltage ripple and
voltage deviation caused by load transients).
If external reference is used, the 3.3-V power supply only needs to meet the requirements specified in the
Recommended Operating Conditions section and the Electrical Characteristics section.
10 Layout
10.1 Layout Guidelines
1. Decoupling capacitors should be placed as close to the device as possible.
2. BPCAP decoupling capacitors should be connected as close as possible to pin D6.
3. MARGIN pins output fast-edge PWM signals. These signals should be routed away from sensitive analog
signals. It is a good practice to place R4 and C1 in Figure 16 as close as possible to the MARGIN pin,
minimizing the propagation distance of the fast-edge PWM signals on the PCB. R3 can be placed near the
power supply feedback node to isolate the feedback node from noise sources on the PCB. If R4 and C1
cannot be located close to the MARGIN pin, add a 20-
Ω to 33-Ω series termination resistor located near the
10.2 Layout Example
UCD90240 is in a 157-pin BGA package. If UCD90240 is mounted on the top layer, decoupling capacitors can
be placed on the bottom layer to make room for top-layer trace routing. The layout example below adopts such a
strategy. Figure 35 shows bottom-layer component placement from top-view. In addition to Figure 35, note that:
1. A uniform ground plane should be used to connect DVSS, AVSS, and VREFA– pins.
2. All four BPCAP pins should be connected to a common internal-layer copper area.
3. AVSS and VREFA– pins can be connected to a common internal-layer copper area.
Copyright © 2015, Texas Instruments Incorporated
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