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UCD90240 Datasheet(Hoja de datos) 11 Page - Texas Instruments

No. de Pieza. UCD90240
Descripción  UCD90240 24-Rail PMBus Power Sequencer and System Manager
Descarga  49 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 11 page
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I2CSCL
I2CSDA
I1
I2
I6
I7
I8
I5
I3
I9
I4
I10
UCD90240
www.ti.com
SLVSCW0 – FEBRUARY 2015
6.7 I
2C/PMBUS Timing Requirements
PARAMETER
MIN
TYP
MAX
UNIT
I1
t(HD:STA)
Start condition hold time
450
ns
I2
t(LOW)
Clock Low period(1)
450
ns
I3
tr
Clock/Data rise time(2)
See (2)
ns
I4
t(HD:DAT)
Data hold time
25
ns
I5
tf
Clock/Data fall time(3)
112.5
125
ns
I6
t(HIGH)
Clock High time
300
ns
I7
t(SU:DAT)
Data setup time
225
ns
I8
t(SU:STA)
Start condition setup time (Repeated start only)
450
ns
I9
t(SU:STO)
Stop condition setup time
300
ns
I10
t(DV)
Data Valid
25
ns
(1)
PMBus host must support clock stretching per PMBus Power System Management Protocol Specification Part I General Requirements,
Transport And Electrical Interface, Revision 1.2, Section 5.2.6.
(2)
Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive Low, the time I2CSCL or
I2CSDA takes to reach a high level depends on external signal capacitance and pullup resistor values.
(3)
Specified at a nominal 50 pF load.
Copyright © 2015, Texas Instruments Incorporated
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