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MC3486N Datasheet(PDF) 4 Page - Texas Instruments |
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MC3486N Datasheet(HTML) 4 Page - Texas Instruments |
4 / 16 page MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS SLLS097C – JUNE 1980 – REVISED FEBRUARY 2002 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VIT + Differential input high-threshold voltage VO = 2.7 V, IO = – 0.4 mA 0.2 V VIT – Differential input low-threshold voltage VO = 0.5 V, IO = – 8 mA – 0.2† V VIK Enable-input clamp voltage II = – 10 mA – 1.5 V VOH High level output voltage VID = 0.4 V, IO = – 0.4 mA, 27 V VOH High-level output voltage ID , O , See Note 4 and Figure 1 2.7 V VOL Low level output voltage VID = – 0.4 V, IO = 8 mA, 05 V VOL Low-level output voltage ID , O , See Note 4 and Figure 1 0.5 V IOZ High impedance state output current VIL = 0.8 V, VID = – 3 V, VO = 2.7 V 40 µA IOZ High-impedance-state output current VIL = 0.8 V, VID = 3 V, VO = 0.5 V – 40 µA VI = – 10 V – 3.25 IIB Differential input bias current VCC = 0 V or 5.25 V, VI = – 3 V –1.5 mA IIB Differential-input bias current CC , Other inputs at 0 V VI = 3 V 1.5 mA VI = 10 V 3.25 IIH High level enable input current VI = 5.25 V 100 µA IIH High-level enable input current VI = 2.7 V 20 µA IIL Low-level enable input current VI = – 0.5 V – 100 µA IOS Short-circuit output current VID = 3 V, VO = 0, See Note 5 – 15 – 100 mA ICC Supply current VIL = 0 85 mA † The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for threshold voltages only. NOTES: 4. Refer to ANSI Standards TIA/EIA-422-B and TIA/EIA-423-B for exact conditions. 5. Only one output should be shorted at a time. switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHL Propagation delay time, high- to low-level output See Figure 2 28 35 ns tPLH Propagation delay time, low- to high-level output See Figure 2 27 30 ns tPZH Output enable time to high level 13 30 ns tPZL Output enable time to low level See Figure 3 20 30 ns tPHZ Output disable time from high level See Figure 3 26 35 ns tPLZ Output disable time from low level 27 35 ns |
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