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AD6634BBC Datasheet(PDF) 51 Page - Analog Devices |
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AD6634BBC Datasheet(HTML) 51 Page - Analog Devices |
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51 / 52 page  REV. 0 AD6634 –51– tSSI CLKn X FRAME SCLK SDI FRAME XXXX A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 47. Serial Word Structure and Serial Port Control Timing JTAG BOUNDARY SCAN The AD6634 supports a subset of IEEE Standard 1149.1 speci- fication. For additional details of the standard, please see “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE-1149 publication from IEEE. The AD6634 has five pins associated with the JTAG interface. These pins are used to access the on-chip Test Access Port and are listed in Table XVIII. All input JTAG pins are pull-up except for TCLK, which is a pull-down. Table XVIII. Boundary Scan Test Pins Name Pin Number Description TRST 67 Test Access Port Reset TCLK 68 Test Clock TMS 69 Test Access Port Mode Select TDI 72 Test Data Input TDO 70 Test Data Output The AD6634 supports six op codes as shown in Table XIX. These instructions set the mode of the JTAG interface. Table XIX. Boundary Scan Op Codes Instruction Op Code IDCODE 001 BYPASS 111 SAMPLE/PRELOAD 010 EXTEST 000 HIGHZ 011 CLAMP 100 The Vendor Identification Code can be accessed through the IDCODE instruction and has the format shown in Table XX. Table XX. Vendor ID Code MSB Part Manufacturing LSB Version Number ID # Mandatory 0000 0010 000 1110 0101 1 0111 1000 1100 A BSDL file for this device is available. Please contact Analog Devices for more information. EXTEST (3'b000)—Places the IC into an external boundary-test mode and selects the boundary-scan register to be connected between TDI and TDO. During this, the boundary-scan register is accessed to drive test data off-chip via boundary outputs and receive test data off-chip from boundary inputs. IDCODE (3'b001)—Allows the IC to remain in its functional mode and selects device ID register to be connected between TDI and TDO. Accessing the ID register does not interfere with the operation of the IC. SAMPLE/PRELOAD (3'b010)—Allows the IC to remain in normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. The boundary-scan register can be accessed by a scan operation to take a sample of the functional data entering and leaving the IC. Also, test data can be preloaded into the boundary scan register before an EXTEST instruction. HIGHZ (3'b011)—Sets all outputs to high impedance state. Selects 1-bit bypass register to be connected between TDI and TDO. CLAMP (3'b100)—Sets the outputs of the IC to logic levels determined by the boundary-scan register and selects 1-bit bypass register to be connected between TDI and TDO. Before this instruction, boundary-scan data can be preloaded with the SAMPLE/PRELOAD instruction. BYPASS (3'b111)—Allows the IC to remain in normal functional mode and selects 1-bit bypass register between TDI and TDO. During this instruction, serial data is transferred from TDI to TDO without affecting operation of the IC. INTERNAL WRITE ACCESS Up to 20 bits of data (as needed) can be written by the process described below. Any high order bytes that are needed are written to the corresponding data registers defined in the external 3-bit address space. The least significant byte is then written to DR0 at address (000). When a write to DR0 is detected, the internal microprocessor port state machine then moves the data in DR2–DR0 to the internal address pointed to by the address in the LAR and AMR. Write Pseudocode void write_micro(ext_address, int data); main(); { / * This code shows the programming of the NCO phase offset register using the write_micro function as defined above. The variable address is the External Address A[2:0] and data is the value to be placed in the external interface register. |
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