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TP3402 Datasheet(PDF) 6 Page - Texas Instruments |
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TP3402 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 17 page  TABLE II Control and Status Register Functions Bit State Control Register Function Status Register Function C7 0 Master Mode Read Back C7 from Control Register 1 Slave Mode Read Back C7 from Control Register C6 0 Deactivate and Power Down Read Back C6 from Control Register 1 Power Up and Activate Read Back C6 from Control Register C5 0 Normal Through Connection Read Back C5 from Control Register 1 Loopback to Digital Interface Read Back C5 from Control Register C4 0 Normal Through Connection Read Back C4 from Control Register 1 Loopback B1aB2aD to Line (Note 1) Read Back C4 from Control Register C3 0 Normal Through Connection Read Back C3 from Control Register 1 Loopback B1 Only to Line (Note 1) Read Back C3 from Control Register C2 0 Normal Through Connection No Error 1 Loopback B2 Only to Line (Note 1) Bipolar Violation Since Last READ (Note 2) C1 0 DCLKDEN pin e 16 kHz Clock Out-Of-Sync 1 DCLKDEN pin e D Channel Enable (Note 3) Loop In-Sync and Activation Complete C0 0 B1B2 Channels Direct No Line Signal at Receiver Input 1 B1B2 Channels Exchanged Line Signal Present at Receiver Input Note 1 Receive data active Note 2 After the device is in sync Note 3 In Master mode only Note 4 C7 is the first bit clocked in and out of the device Timing Diagrams TLH9264 – 6 FIGURE 6 B Channel Interface Timing Master Mode 6 |
Número de pieza similar - TP3402 |
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Descripción similar - TP3402 |
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