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TPIC6A259DWRG4 Datasheet(PDF) 1 Page - Texas Instruments

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No. de Pieza. TPIC6A259DWRG4
Descripción  POWER LOGIC 8-BIT ADDRESSABLE LATCH
Descarga  13 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPIC6A259DWRG4 Datasheet(HTML) 1 Page - Texas Instruments

 
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TPIC6A259
POWER LOGIC 8BIT ADDRESSABLE LATCH
SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Low r
DS(on) ...1 Ω Typ
Output Short-Circuit Protection
Avalanche Energy . . . 75 mJ
Eight 350-mA DMOS Outputs
50-V Switching Capability
Four Distinct Function Modes
Low Power Consumption
description
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage appli-
cations in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS
transistor
features
an
independent
chopping
current-limiting
circuit
to
prevent
damage in the case of a short circuit.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.
Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.
OUTPUT OF
ADDRESSED
DRAIN
EACH
OTHER
DRAIN
INPUTS
FUNCTION
CLR G
FUNCTION TABLE
LATCH SELECTION TABLE
SELECT INPUTS
DRAIN
ADDRESSED
0
1
2
3
4
5
6
7
L
L
L
L
H
H
H
H
D
H
H
L
L
H
L
L
H
Qio
Qio
Qio
Qio
H
H
X
Memory
L
L
L
L
H
L
L
H
H
H
8-Line
Demultiplexer
LH
X
H
H
Clear
Addressable
Latch
S2
S1
S0
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DRAIN2
DRAIN3
S1
LGND
PGND
PGND
S2
G
DRAIN4
DRAIN5
DRAIN1
DRAIN0
S0
VCC
PGND
PGND
CLR
D
DRAIN7
DRAIN6
NE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DRAIN2
DRAIN3
S1
LGND
PGND
PGND
PGND
PGND
S2
G
DRAIN4
DRAIN5
DRAIN1
DRAIN0
S0
VCC
PGND
PGND
PGND
PGND
CLR
D
DRAIN7
DRAIN6
DW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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