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TPIC44H01 Datasheet(PDF) 4 Page - Texas Instruments

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No. de pieza TPIC44H01
Descripción Electrónicos  4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
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TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
PIN
PIN
I/O
DESCRIPTION
NO.
NAME
I/O
DESCRIPTION
1
CS
I
Chip Select. CS is an active low, logic level input with internal pullup. A logic level low on CS enables the
serial interface and refreshes the fault interrupt (FLT). A high on CS enables the serial register to serve as
the fault data register.
2
SDO
O
Serial Data Output. SDO is a logic level, tri-state output that transfers fault data to the host controller. Serial
input data passes to the next stage for cascade operation. SDO is forced into a high impendance state when
CS terminal is in a high state. When CS is in a low state, data is clocked out on each falling edge of SCLK.
3
SDI
I
Serial Data Input. SDI is a logic level input with hysteresis and internal pulldown. Gate drive output control
data is clocked into the serial register using SDI. A high SDI bit programs a particular gate output on, and a
low turns it off, as long as the parallel input is off (OR function).
4
SCLK
I
Serial Clock. SCLK is a logic level input with hysteresis and internal pulldown. SCLK clocks data at the SDI
terminal into the input serial shift register on each rising edge, and shifts out fault data (and serial input data
for cascaded operation) to the SDO pin on each falling edge.
5
AR_ENBL
I
Auto-Retry Enable. AR_ENBL is a logic level input with hysteresis and internal pulldown. When
AR_ENBL=0, an over-current/short-to-ground fault latches the channel off. When AR_ENBL = 1, an
over-current/short-to-ground fault engages a low duty cycle operation.
6
GND
I
Analog ground and substrate connection
7–10
IN1-4
I
Parallel Inputs. IN1-4 are logic level inputs with hysteresis and internal pulldown. IN1–4 provide real-time
control of gate pre-drive circuitry. A high on IN1-4 will turn on corresponding gate drive outputs (GATE1-4).
Gate output status is a logic OR function of the parallel inputs and the serial input bits.
11
VCC
I
5-V logic supply voltage
12
V(PK_A)
I
Dynamic over-current fault threshold peak voltage that is shared by channels 1 and 2
13
V(PK_B)
I
Dynamic over-current fault threshold peak voltage that is shared by channels 3 and 4
14–17
V(COMP1-4)
I
Fault Reference Voltage. V(COMP1–4) are used to provide an external fault reference voltage for the
over-current fault detection circuitry. It is also used to generate a dynamic threshold when used in conjunction
with V(PK_x). To guarantee V(COMP) stability, a minimum of 100 pF capacitance should be placed from
V(COMP) to ground.
18
RESET
I
Reset. RESET is an active low, logic level input with hysteresis and internal pullup. A low on RESET clears
all registers and fault bits. All gate outputs are turned off and a latched FLT interrupt is cleared.
19
FLT
O
Fault Interrupt. FLT is an active low, logic level, open-drain output providing real-time latched fault interrupts
for fault detection. A latched FLT is cleared only by a low on CS. The FLT terminal can be OR’ed with other
devices for fault interrupt handling. An external pullup is required.
20, 22,
24, 26
SRC1-4
I
FET Source Inputs. These inputs are used for both open-load and over-current fault detection at the source
of the external FETs.
21, 23,
25, 27
GATE1-4
O
Gate Drive Outputs. Output voltage is derived from V(CP) supply voltage. Internal clamps prevent the voltage
on these nodes, with respect to SRC1-4, from exceeding the VGS rating of most FETs.
28
V(CP)
O
Charge pump voltage storage capacitor and supply pin to high-side gate drives
29
CP2
O
Charge pump capacitor terminal
30
CP1
O
Charge pump capacitor terminal
31
V(PWR)
I
Power supply voltage input
32
PGND
I
Power ground for charge pump


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