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TPS3307-18-EP Datasheet(PDF) 6 Page - Texas Instruments |
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TPS3307-18-EP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 18 page TPS330718EP, TPS330733EP TRIPLE PROCESSOR SUPERVISORS SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw Pulse width SENSEn VSENSEnL = VIT− −0.2 V, VSENSEnH = VIT+ + 0.2 V 6 µs tw Pulse width MR VIH = 0.7 × VDD,VIL = 0.3 × VDD 100 ns switching characteristics at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td Delay time VI(SENSEn) ≥ VIT+ + 0.2 V, MR ≥ 0.7 × VDD, See timing diagram 140 200 280 ms tPHL Propagation (delay) time, high-to-low level output MR to RESET VI(SENSEn) ≥ VIT+ + 0.2 V, 200 600 ns tPLH Propagation (delay) time, low-to-high level output MR to RESET VI(SENSEn) ≥ VIT+ + 0.2 V, VIH = 0.7 × VDD,VIL = 0.3 × VDD 200 600 ns tPHL Propagation (delay) time, high-to-low level output SENSEn to RESET VIH ≥ VIT+ + 0.2 V, VIL ≤ VIT− − 0.2 V, 1 5 s tPLH Propagation (delay) time, low-to-high level output SENSEn to RESET VIH ≥ VIT+ + 0.2 V, VIL ≤ VIT− − 0.2 V, MR ≥ 0.7 × VDD 1 5 µs |
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