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TPS3126E12DBVT Datasheet(PDF) 6 Page - Texas Instruments

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No. de Pieza. TPS3126E12DBVT
Descripción  ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
Descarga  21 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS3126E12DBVT Datasheet(HTML) 6 Page - Texas Instruments

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TPS3123-xx
TPS3124-xx, TPS3125-xx
TPS3126-xx, TPS3128-xx
SLVS227E
– AUGUST 1999 – REVISED AUGUST 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
at specified temperature range.
MIN
MAX
UNIT
TA = 0°C to +85°C
0.75
3.3
VDD
Supply voltage
V
TA = –40°C to +85°C
0.85
3.3
VDD
Manual reset voltage
0.0
VDD +0.3
V
VWD1
Watchdog input voltage
0
VDD +0.3
V
VIH
High-level input voltage
0.7
×VDD
V
VIL
Low-level input voltage
0.3
×VDD
V
Δ t/ΔV
Input transition rise and fall rate at WDI
1
μs/V
TA
Operating free-air temperature range
40
+85
°C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MR pullup resistor (internal)
27
k
WDI
WDI = VDD = 3.3 V
1
1
IIH
High-level input current
μA
MR
MR = 0.7
× VDD,
VDD = 3.3 V
20
55
WDI
WDI = 0 V,
VDD = 3.3 V
1
1
IIL
Low-level input current
μA
MR
MR = 0 V,
VDD = 3.3 V
80
170
High-level output current
TPS3126-xx,
IOH
VDD = VOH = 3.3 V
200
nA
(leakage into RESET pin)
TPS3128-xx
VDD = 1.5 V,
IOH = –1 mA
RESET
VDD = 3.3 V,
IOH = –4.5 mA
High-level output voltage
VOH
0.8
×VDD
V
(TPS3123/4/5 only)
VDD = 0.75 V,
IOH = –8 μA
RESET
VDD = 1.5 V,
IOH = –1 mA
VDD = 0.75 V,
IOL = 15 μA
RESET
VDD = 1.5 V,
IOL = 1.4 mA
0.2
× VDD
VOL
Low-level output voltage
V
VDD = 1.5 V,
IOL = 1.4 mA
RESET
VDD = 3.3 V,
IOL = 3 mA
0.4
TPS312xJ12
1.04
1.08
1.12
TPS312xG15
1.35
1.40
1.45
TPS312xJ18
1.56
1.62
1.68
Negative-going input threshold
VIT–
TPS312xL30
TA = –40°C to +85°C
2.57
2.64
2.71
V
voltage (1)
TPS312xE12
1.10
1.14
1.18
TPS312xE15
1.38
1.43
1.48
TPS312xE18
1.65
1.71
1.77
1 V
< VIT– < 1.4 V
15
Vhys
Hysteresis at VDD input
1.4 V
< VIT– < 2 V
20
mV
2 V
< VIT– < 3 V
30
TPS3123-xx
VDD = 0.75 V
14
WDI = VDD,
TPS3124-xx
MR unconnected
VDD = 3.3 V
22
30
TPS3128-xx
IDD
Supply current
μA
VDD = 0.75 V
14
TPS3125-xx
MR unconnected
TPS3126-xx (2)
VDD = 3.3 V
18
25
Ci
Input capacitance at MR, WDI
VI = 0 V to 3.3 V
5
pF
(1)
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
μF) should be placed near the supply terminal.
(2)
The supply current during delay time td is typical 5 μA higher.
6
Copyright
© 1999–2011, Texas Instruments Incorporated


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