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TPS389015DSER Datasheet(PDF) 11 Page - Texas Instruments |
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TPS389015DSER Datasheet(HTML) 11 Page - Texas Instruments |
11 / 25 page TPS389001 Adjustable Version V DD MR SENSE RESET CT GND 1.15 V V REF Reset Logic Timer Fixed Voltage Version Adjustable Voltage Version V DD MR SENSE RESET CT GND 1.15 V V REF Reset Logic Timer R 2 R 1 Copyright © 2016, Texas Instruments Incorporated 11 TPS3890 www.ti.com SLVSD65A – MARCH 2016 – REVISED MAY 2016 Product Folder Links: TPS3890 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The TPS3890 supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below VITN or the manual reset (MR) is driven low. The RESET output remains asserted for a user- adjustable time after both the manual reset (MR) and SENSE voltages return above their respective thresholds. 8.2 Functional Block Diagram 8.3 Feature Description The combination of user-adjustable reset delay time with a broad range of threshold voltages allow these devices to be used in a wide array of applications. Fixed negative threshold voltages (VITN) can be factory set from 1.15 V to 3.17 V (see the Device Comparison Table for available options), and the adjustable device can be used to customize the threshold voltage for other application needs by using an external resistor divider. The CT pin allows the reset delay to be set between 25 μs and 30 s with the use of an external capacitor. 8.3.1 User-Configurable RESET Delay Time The rising RESET delay time (tPD(r)) can be configured by installing a capacitor connected to the CT pin. The TPS3890 uses a CT pin charging current (ICT) of 1.15 µA to help counter the effect of capacitor and board-level leakage currents that can be substantial in certain applications. The rising RESET delay time can be set to any value between 25 µs (no CCT installed) and 30 s (CCT = 26 µF). The capacitor value needed for a given delay time can be calculated using Equation 1: tPD(r) (sec) = CCT × VCT ÷ ICT+ tPD(r)(nom) (1) The slope of Equation 1 is determined by the time that the CT charging current (ICT) takes to charge the external capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged through the internal CT pulldown resistor (RCT). When the RESET conditions are cleared, the internal precision current source is enabled and begins to charge the external capacitor and when the voltage on this capacitor reaches 1.22 V, RESET is deasserted. Note that in order to minimize the difference between the calculated RESET delay time and the actual RESET delay time, use a low-leakage type capacitor (such as a ceramic capacitor) and minimize parasitic board capacitance around this pin. |
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