TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999

5

POST OFFICE BOX 655303

detailed description (continued)

droop compensation

resistor divider, and connected to DROOP.

inhibit

INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers

are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart

capacitor is released and normal converter operation begins. When the system-logic supply is connected to

INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply

exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either

5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold

is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.

during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is

normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise

immunity.

slowstart

ANAGND and is charged by an internal current source. The current source is proportional to the reference

the same value for all VID settings. The slowstart charging current is determined by the following equation:

setting the slowstart time is:

(seconds)

power good

pin is pulled low. PWRGD is an open-drain output.

overvoltage protection

undervoltage lockout value. A 3-

µs deglitch timer is included for noise immunity. Refer to the LODRV section

for information on how to protect the microprocessor against overvoltages due to a shorted fault across the

high-side power FET.