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TPS72101DBVR Datasheet(PDF) 2 Page - Texas Instruments |
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TPS72101DBVR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 14 page TPS72101, TPS72115 TPS72116, TPS72118 SLVS352B – DECEMBER 2001 – REVISED MAY 2002 www.ti.com 2 Thesedevices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ VOLTAGE PACKAGE PART NUMBER SYMBOL Adjustable TPS72101DBVT(1) TPS72101DBVR(2) PEKI 40 °Cto125°C 1.5 V SOT-23 TPS72115DBVT(1) TPS72115DBVR(2) PEII –40 °C to 125°C 1.6 V SOT 23 (DBV) TPS72116DBVT(1) TPS72116DBVR(2) PHFI 1.8 V TPS72118DBVT(1) TPS72118DBVR(2) PEJI (1) The DBVT indicates tape and reel of 250 parts. (2) The DBVR indicates tape and reel of 3000 parts. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS72101,TPS72115 TPS72116, TPS72118 Input voltage range(2) – 0.3 V to 7 V Voltage range at EN –0.3 V to 7 V Voltage on OUT, FB, NC –0.3 V to VI + 0.3 V Peak output current Internallylimited ESD rating, HBM 3 kV Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, TJ – 40 °C to 150°C Storage temperature range, Tstg – 65 °C to 150°C (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. PACKAGE DISSIPATION RATING BOARD PACKAGE R θJC R θJA DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING Low K(1) DBV 65.8 °C/W 259 °C/W 3.9 mW/ °C 386 mW 212 mW 154 mW High K(2) DBV 65.8 °C/W 180 °C/W 5.6 mW/ °C 555 mW 305 mW 222 mW (1) TheJEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2 ounce copper traces on top of theboard. (2) The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. |
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