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TPS54872PWPR Datasheet(PDF) 11 Page - Texas Instruments |
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TPS54872PWPR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 22 page  TPS54872 SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 www.ti.com 11 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 8 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under the device package. Minimum recommended exposed copper area for powerpad. 5 mm stencils may required 10 percent larger area. Minimum recommended thermal vias: 8 x .013 dia. inside powerpad area 4 x .018 dia. under device as shown. Additional .018 dia. vias may be used if top side Analog Ground ar ea is extended. 8 PL ∅ 0.0130 4 PL ∅ 0.0180 Connect Pin 1 to Analog Ground plane in this area for optimum performance Minimum recommended top side Analog Ground area 0.0339 0.0650 0.0500 0.0500 0.0500 0.0650 0.0339 0.3820 0.0150 0.06 0.2090 0.0256 0.1700 0.1340 0.0603 0.0400 0.3478 Figure 9. Recommended Land Pattern for 28-Pin PWP PowerPAD |
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