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TPS54873PWPR Datasheet(PDF) 9 Page - Texas Instruments |
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TPS54873PWPR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 23 page  TPS54873 SLVS444A − OCTOBER 2002 − REVISED FEBRUARY 2005 www.ti.com 9 OPERATING FREQUENCY In the application circuit, the RT pin is grounded through a 71.5-kΩ resistor (R6) to select the operating frequency of 700 kHz. To set a different frequency, place a 68-kΩ to 180-kΩ resistor between RT (pin 28) and analog ground or leave RT floating to select the default of 350 kHz. The resistance can be approximated using the following equation: R + 500 kHz Switching Frequency 100 [kW] OUTPUT FILTER The output filter is composed of a 0.65-µH inductor (L1) and 3 x 22-µF capacitors (C5, C7 and C8). The inductor is a low dc resistance (.017 Ω) type, Pulse PA0277 0.65 µH. The capacitors used are 22-µF, 6.3-V ceramic types with X5R dielectric. An additional high frequency bypass capacitor, C13 is also used. PRECHARGE CIRCUIT VIN precharges the output of the application circuit through series diodes (D1 and D2) during start-up. As the input voltage increases at start-up, the output is precharged to VIN minus the forward bias voltage of the two diodes. When the internal reference has ramped up to a value greater than the voltage fed back to the VSENSE pin, the output of the internal error amplifier begins to increase. When this output reaches the maximum ramp amplitude, the output of the PWM comparator reaches 100 percent duty cycle and the internal logic enables the high-side FET driver and switching begins. The output tracks the internal reference until the preset output voltage is reached. Under no circumstances should the precharge voltage be allowed to increase above the preset output value. PCB LAYOUT Figure 10 shows a generalized PCB layout guide for the TPS54873 The VIN pins are connected together on the printed-circuit board (PCB) and bypassed with a low-ESR ceramic-bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54873 ground pins. The minimum recommended bypass capacitance is 10-µF ceramic capacitor with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins. The TPS54873 has two internal grounds (analog and power). Inside the TPS54873, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54873, particularly at higher output currents. Ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground traces are recommended. There is an area of ground on the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Additional vias are also used at the ground side of the input and output filter capacitors. The AGND and PGND pins are tied to the PCB ground by connecting them to the ground area under the device as shown. The only components that tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54873. Use a separate wide trace for the analog ground signal path. The analog ground is used for the voltage set point divider, timing resistor RT, slow-start capacitor and bias capacitor grounds. Connect this trace directly to AGND (Pin 1). The PH pins are tied together and routed to the output inductor. Since the PH connection is the switching node, the inductor is located close to the PH pins. The area of the PCB conductor is minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, LOUT, COUT and PGND as small as practical. Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC package and the device pin-out, they must be routed close, but maintain as much separation as possible while still keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency, connect them to this trace. If pre−charge diodes are used, keep the path from the voltage source to the output filter capacitor short. Make sure the etch is wide enough to carry the pre−charge current. (1) |
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