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TPS40222 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS40222 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 46 page  DEVICE INFORMATION PIN CONNECTIONS 1 2 3 4 16 15 14 13 PVDD2 BOOT2 SW2 BP PVDD1 BOOT1 SW1 GND 5 6 7 12 11 10 SEQ ILIM2 FB2 EN1 EN2 FB1 Thermal Pad (bottom side) HTSSOP (PWP) (Top View) 8 9 COMP2 COMP1 TPS55383 ,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is BOOT1 2 I turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is BOOT2 15 I turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7- µF BP 13 - to 10- µF X7R or X5R) ceramic capacitor. Output of Error Amplifier for Output 1. A series connected R-C network from this pin to GND serves to COMP1 8 O compensate the feedback loop. See Feedback Loop Compensation Component Selection for further information. Output of Error Amplifier for Output 2. A series connected R-C network from this pin to GND serves to COMP2 9 O compensate the feedback loop. See Feedback Loop Compensation Component Selection for further information. Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft start of EN1 5 I Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft start of EN2 6 I Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from FB1 7 I Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided externally to the device. See Feedback Loop Compensation Component Selection section for further information. Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from FB2 10 I Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated Output voltage. Compensation for the feedback loop is provided externally to the device. See Feedback Loop Compensation Component Selection section for further information. GND 4 - Ground pin for the device. Connect directly to Thermal Pad. Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetrical load currents (Output 1 load current much greater than Output 2 load current) to optimize component ILIM2 11 I scaling of the lower current output while maintaining proper component derating in a overcurrent fault condition. The discrete levels are available as shown in Table 2, Current Limit Threshold Adjustment for Output 2. Note: An internal 2-resistor divider (150-k Ω each) connects BP to ILIM2 and to GND. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386 |
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