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TPS61252DGST Datasheet(PDF) 9 Page - Texas Instruments
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TPS61252DGST Datasheet(HTML) 9 Page - Texas Instruments
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SLVSAG3A – SEPTEMBER 2010 – REVISED DECEMBER 2014
10.3 Feature Description
The TPS61252 boost converter operates as a quasi-constant frequency adaptive on-time controller. In a typical
application, the frequency is 3.25 MHz and is defined by the input to output voltage ratio and does not vary from
moderate to heavy load currents. At light load currents, the converter automatically enters Power Save Mode and
operates in PFM (Pulse Frequency Modulation) mode. During pulse-width-modulation (PWM) operation, the
converter uses a unique fast response quasi-constant on-time valley current mode controller scheme which
offers very good line and load regulation allowing the use of small ceramic input and output capacitors.
Based on the V
ratio, a simple circuit predicts the required on-time. At the beginning of the switching
cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined
by the on-time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on
and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by
setting the on-timer again and activating the low-side N-MOS switch.
The TPS61252 controls the input current through an intelligent adjustment of a valley current limit that corrects
the value in a way that it almost turns out as an average input current limit. The current can be adjusted with an
accuracy of ±20%.
This architecture with adaptive slope compensation provides excellent transient load response and requires
minimal output filtering. Internal softstart and loop compensation simplifies the design process, while minimizing
the number of external components.
10.3.2 Current Limit Operation
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off
time, through sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced when the power stage of the device operates in a constant current mode. The
maximum continuous output current (I
), before entering current limit (CL) operation, can be defined by
The duty cycle (D) can be estimated by Equation 2:
and the peak-to-peak current ripple (
) is calculated by Equation 3:
The output current, I
, is the average of the rectifier current waveform. When the load current is increased
such that the lower peak is above the current limit threshold, the off-time is increased to allow the current to
decrease to this threshold before the next on-time begins. When the current limit is reached, the output voltage
decreases if the load is further increased.
The TPS61252 has an internal softstart circuit that controls the ramp-up of the current during start-up and
prevents the converter from inrush current that exceeds the set current limit. The current is ramped to the set
current limit in typical 100 µs . After reaching the current limit threshold, it stays there until V
converter starts switching and boosting up the voltage to its nominal output voltage. During the complete start-up,
the input current does not exceed the current limit that is set by resistor R
The device is enabled by setting the EN pin to a voltage above 1 V. At first, the internal reference is activated
and the internal analog circuits are settled. After typically 50 µs, the output voltage ramps up, controlled by the
softstart circuitry. The output voltage reaches its nominal value as fast as the current limit settings and the load
condition allows it.
Copyright © 2010–2014, Texas Instruments Incorporated
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