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TPS61300YFFR Datasheet(HTML) 30 Page - Texas Instruments
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> 400 mV)
TPS61305, TPS61305A, TPS61306
SLVS957E – JUNE 2009 – REVISED APRIL 2016
Product Folder Links: TPS61300 TPS61301 TPS61305
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Copyright © 2009–2016, Texas Instruments Incorporated
Figure 43. Storage Capacitor, Simple Adaptive Precharge Voltage
8.3.16 Serial Interface Description
C is a 2-wire serial interface. The bus consists of a data line (SDA) and a clock line (SCL) with pullup
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I
C compatible devices connect
to the I
C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital
signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives or transmits data on the bus under control of the master device.
The TPS6130xx device works as a slave and supports the following data transfer modes, as defined in the I
Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps). The
interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values
depending on the instantaneous application requirements. Register contents remain intact as long as supply
voltage remains above 2.1 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-
mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-
mode. The TPS6130xx device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7-bit address is defined as 011 0011.
8.4 Device Functional Modes
8.4.1 Down-Mode in Voltage Regulation Mode
In general, a boost converter only regulates output voltages which are higher than the input voltage. The featured
devices come with the ability to regulate 4.2 V at the output with an input voltage being has high as 5.5 V. To
control these applications properly, a down-conversion mode is implemented.
In voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to
the down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets
the voltage drop across the PMOS as high as needed to regulate the output voltage. This means the power
losses in the converter increase. This must be considered for thermal consideration. The down-conversion mode
is automatically turned off as soon as the input voltage falls about 200 mV below the output voltage.
For proper operation in down-conversion mode, the output voltage must not be programmed higher than
Take care not to violate the absolute maximum ratings at the SW pins.
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