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TPS61300YFFR Datasheet(PDF) 37 Page - Texas Instruments

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No. de Pieza. TPS61300YFFR
Descripción  TPS6130xx 1.5-A and 4.1-A Multiple LED Camera Flash Driver With I2C Compatible Interface
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Fabricante  TI1 [Texas Instruments]
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TPS61300YFFR Datasheet(HTML) 37 Page - Texas Instruments

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START Condition
STOP Condition
TPS61300, TPS61301
TPS61305, TPS61305A, TPS61306
Product Folder Links: TPS61300 TPS61301 TPS61305
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Copyright © 2009–2016, Texas Instruments Incorporated
The integrated discharge resistor has a typical resistance of 2 k
Ω equally split-off between VOUT to BAL and
BAL to GND outputs. The required time to discharge the output capacitor at VOUT depends on load current and
the effective output capacitance. The active balancing circuit is disabled and the device consumes only a
shutdown current of 1
μA (typical).
In high-current mode (HC_SEL = H), the device maintains its output biased at the input voltage level. In this
mode, the synchronous rectifier is current-limited, allowing external load, such as audio amplifiers, to be powered
with a restricted supply. The active balancing circuit is enabled and the device consumes only a standby current
of 5
μA (typical).
8.4.10 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 160°C typical, the device goes into thermal shutdown. In this
mode, the power stage and the low-side current regulators are turned off, the HOTDIE[1:0] bits are set and can
only be reset by a readout.
In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device continues its operation when
the junction temperature falls below 140°C (typical) again. In the current regulation mode (that is, DC light or
flashlight modes) the device operation is suspended.
8.4.11 F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 54. All I2C-compatible devices will
recognize a start condition.
Figure 54. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 55). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 56) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
Figure 55. Bit Transfer On the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

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