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TPS61300YFFR Datasheet(PDF) 39 Page - Texas Instruments

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No. de Pieza. TPS61300YFFR
Descripción  TPS6130xx 1.5-A and 4.1-A Multiple LED Camera Flash Driver With I2C Compatible Interface
Descarga  70 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS61300YFFR Datasheet(HTML) 39 Page - Texas Instruments

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Slave Address
R/W
A
Register Address
A
P
Sr
1
7
1
1
1
1
8
Data
8
A/A
1
S
HS-MasterCode
A
1
1
8
F/SMode
HSMode
F/SMode
Data Transferred
(nxBytes + Acknowledge)
HSModeContinues
Slave Address
Sr
FromMasterto TPS6130x
From TPS6130xtoMaster
A
= Acknowledge
A
= Acknowledge
S
= START condition
Sr
= REPEATEDSTART condition
P
= STOP condition
Slave Address
R/W
A
Register Address
A
Data
A
P
S
1
7
1
1
1
1
1
8
8
“0” Write
Sr
1
Slave Address
R/W
7
1
“1” Read
A
1
FromMasterto TPS6130x
From TPS6130xtoMaster
A
= Acknowledge
S
= START condition
Sr
= REPEATEDSTART condition
P
= STOP condition
Slave Address
R/W
A
Register Address
A
Data
A
P
S
1
7
1
1
1
1
1
8
8
“0” Write
FromMasterto TPS6130x
From TPS6130xtoMaster
A
= Acknowledge
S
= START condition
Sr
= REPEATEDSTART condition
P
= STOP condition
39
TPS61300, TPS61301
TPS61305, TPS61305A, TPS61306
www.ti.com
SLVS957E – JUNE 2009 – REVISED APRIL 2016
Product Folder Links: TPS61300 TPS61301 TPS61305
Submit Documentation Feedback
Copyright © 2009–2016, Texas Instruments Incorporated
8.4.13 TPS6130xx I2C Update Sequence
The TPS6130xx requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6130xx device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6130xx. TPS6130xx performs an
update on the falling edge of the acknowledge signal that follows the LSB byte.
Figure 58. Write Data Transfer Format in F/S-Mode
Figure 59. Read Data Transfer Format in F/S-Mode
Figure 60. Data Transfer Format in HS-Mode
8.5 Register Maps
8.5.1 Slave Address Byte
Figure 61. Slave Address Byte Description
MSB
LSB
X
X
X
X
X
X
A1
A0
The slave address byte is the first byte received following the START condition from the master device.
8.5.2 Register Address Byte
Figure 62. Register Address Byte Description
MSB
LSB
0
0
0
0
00
D2
D1
D0


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