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TPS61280AYFFT Datasheet(PDF) 5 Page - Texas Instruments

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No. de Pieza. TPS61280AYFFT
Descripción  TPS6128xA Low-, Wide- Voltage Battery Front-End DC/DC Converter Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications
Descarga  54 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS61280AYFFT Datasheet(HTML) 5 Page - Texas Instruments

 
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SW
PGND
AGND
PGND
SW
nBYP
AGND
PGND
TOP VIEW
D4
D3
D2
D1
C4
PGND
C3
C2
C1
nBYP
PGND
SW
AGND
AGND
BOTTOM VIEW
VSEL
MODE
VOUT
VOUT
VOUT
B1
B2
B3
B4
VOUT
VSEL
MODE
EN
PG
VIN
VIN
VIN
A1
A2
A3
A4
VIN
EN
PG
SW
PGND
TPS61280A, TPS61281A, TPS61282A
www.ti.com
SLVSCG9A – MAY 2014 – REVISED SEPTEMBER 2014
(TPS6128xA)
Pin Functions - TPS6128xA
PIN
I/O
DESCRIPTION
NAME
NO.
VIN
A3, A4
I
Power supply input.
VOUT
B3, B4
O
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the
converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit
EN
A1
I
the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For
more details, refer to .
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to Table 2.
Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output
voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage
PG
A2
O
out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes
proper operation.
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
VSEL
B1
I
floating and must be terminated.
A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to Table 2. This
nBYP
C1
I
pin must not be left floating and must be terminated.
This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be
connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates
that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by
applying a high level on this pin.
MODE
B2
I
MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load
currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during
device start-up.
MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.
SW
C3, C4
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
PGND
D2, D3, D4
Power ground pin.
AGND
C2, D1
Analog ground pin. This is the signal ground reference for the IC.
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: TPS61280A TPS61281A TPS61282A


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