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Si5340B-D-GM Datasheet(PDF) 8 Page - Silicon Laboratories |
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Si5340B-D-GM Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 53 page 3.3.3 Input Selection (IN0, IN1, IN2, XA/XB) The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input selection as pin or register selectable. There are internal pull ups on the IN_SEL pins. Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins IN_SEL[1:0] Selected Input 0 0 IN0 0 1 IN1 1 0 IN2 1 1 XA/XB 3.4 Fault Monitoring The Si5340/41-D provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of lock (LOL) for the PLL as shown in the figure below. PLL LPF PD Mn IN0 IN0b LOS0 ÷P0 IN1 IN1b ÷P1 FB_IN FB _INb IN2 IN2b ÷P2 LOL Si5341/40 XB XA OSC ÷Pfb Md ÷ LOSXAB LOS1 LOS2 LOSFB Figure 3.4. LOS and LOL Fault Monitors 3.4.1 Status Indicators The state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOLb). Each of the status indicator register bits has a corresponding sticky bit in a separate register location. Once a status bit is asserted its corre- sponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic zero to a sticky register bit clears its state. 3.4.2 Interrupt Pin (INTRb) An interrupt pin (INTRb) indicates a change in state with any of the status registers. All status registers are maskable to prevent asser- tion of the interrupt pin. The state of the INTRb pin is reset by clearing the status registers. Si5341/40 Rev D Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 7 |
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