Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

Si5347C-D-GM Datasheet(PDF) 6 Page - Silicon Laboratories

No. de pieza Si5347C-D-GM
Descripción Electrónicos  Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators
Download  55 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

Si5347C-D-GM Datasheet(HTML) 6 Page - Silicon Laboratories

Back Button Si5347C-D-GM Datasheet HTML 2Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 3Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 4Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 5Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 6Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 7Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 8Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 9Page - Silicon Laboratories Si5347C-D-GM Datasheet HTML 10Page - Silicon Laboratories Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 55 page
background image
3.3.5 Holdover Mode
Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input
clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the
disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up
to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is
calculated from a programmable window within the stored historical frequency data. Both the window size and delay are programmable,
as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignor-
ing frequency data that may be corrupt just before the input clock failure.
Programmable delay
Clock Failure and
Entry into Holdover
time
0s
Historical Frequency Data Collected
Programmable historical data window
used to determine the final holdover value
120s
1s,10s, 30s, 60s
30ms, 60ms, 1s,10s, 30s, 60s
Figure 3.2. Programmable Holdover Window
When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in
Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the
XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input
clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in
process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register program-
mable.
Add new section The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated,
the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and
a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any
of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to
ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more
information on ramped input switching, see 3.6.6 Ramped Input Switching.
Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable
holdover exit BW.
3.4 Digitally-Controlled Oscillator (DCO) Mode
The DSPLLs support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words
(FSW).The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or dec-
rement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO
mode is available when the DSPLL is operating in either Free-run or Locked Mode.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 5


Número de pieza similar - Si5347C-D-GM

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Skyworks Solutions Inc.
SI5347C-D-GM SKYWORKS-SI5347C-D-GM Datasheet
879Kb / 56P
   Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators
Rev. 1.1
More results

Descripción similar - Si5347C-D-GM

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Silicon Laboratories
SI5347 SILABS-SI5347 Datasheet
2Mb / 59P
   DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS
logo
Skyworks Solutions Inc.
SI5347 SKYWORKS-SI5347 Datasheet
879Kb / 56P
   Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators
Rev. 1.1
SI5397 SKYWORKS-SI5397 Datasheet
1Mb / 60P
   Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators
Rev. 1.2
logo
Silicon Laboratories
SI5341 SILABS-SI5341 Datasheet
2Mb / 56P
   LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR
SI5345 SILABS-SI5345_16 Datasheet
1Mb / 60P
   10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
SI5345 SILABS-SI5345 Datasheet
1Mb / 62P
   10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER
logo
Skyworks Solutions Inc.
SI5391 SKYWORKS-SI5391 Datasheet
1Mb / 45P
   Ultra Low-Jitter, 12-Output, Any-Frequency, Any-Output Clock Generator
Rev. 0.7
SI5345 SKYWORKS-SI5345 Datasheet
976Kb / 58P
   10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
Rev. 1.2
SI5334 SKYWORKS-SI5334 Datasheet
1Mb / 37P
   PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR
Rev. 1.3
SI5341 SKYWORKS-SI5341 Datasheet
1Mb / 49P
   Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator
Rev. 1.1
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com