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SI5380 Datasheet(PDF) 7 Page - Silicon Laboratories |
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SI5380 Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 53 page 3.1.5 Modes of Operation Once initialization is complete, the Si5380 operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail. No valid input clocks selected Lock Acquisition (Fast Lock) Locked Mode Holdover Mode Phase lock on selected input clock is achieved An input is qualified and available for selection No valid input clocks available for selection Free-run Valid input clock selected Reset and Initialization Power-Up Selected input clock fails Yes No Holdover History Valid? Other Valid Clock Inputs Available? No Yes Input Clock Switch Figure 3.2. Modes of Operation 3.1.6 Initialization and Reset When power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa- tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM and all circuits, including the serial interface, will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. 3.1.7 Freerun Mode Once power is applied to the Si5380 and initialization is complete, the device will automatically enter freerun mode. Output clocks will be generated on the outputs with their configured frequencies. The frequency accuracy of the generated output clocks in freerun mode is dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal fre- quency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any change or drift of the crystal frequency or external reference on the XA/XB pins will be tracked at the output clock frequencies. 3.1.8 Lock Acquisition If a valid input clock is selected for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock fea- ture is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Band- width setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. Si5380 Rev D Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 6 |
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