PRODUCT SPECIFICATION

FAN5068

8

REV. 1.0.1 9/9/04

Circuit Description

Overview

Control Functions

S3#I, EN Input Threshold

1.0

1.25

1.55

V

S3#I EN Input Current

–1

1

µA

Over-Temperature Shutdown

150

°C

Over-Temperature Hysteresis

25

°C

170

300

Ω

S3#O Output High Leakage

V(S3#O) = 12V

4

10

µA

SBSW Output Low Resistance

5V MAIN OK

125

200

Ω

SBSW Sink current (note 1)

5V MAIN < UVLO

500

nA

SBSW Output High (note 2)

820

1200

Ω

Recommended operating conditions, component values per Figure 1 unless otherwise noted.

Parameter

Conditions

Min.

Typ.

Max.

Units

The FAN5068 provides 5 functions:

1.

A general purpose PWM regulator, typically used to gen-

erate VDDQ for DDR memory.

2.

A low-dropout linear VTT regulator capable of sinking

and sourcing 1.5A peak.

3.

An adjustable Ultra Low Drop Out (ULDO) controller

which, in conjunction with an external N-Channel power

MOSFET, provides a programmable low voltage output.

The power source for this output is typically the VDDQ

output and is used to provide the 1.2V GTL

processor FSB termination voltage.

4.

Control for generating a 5V DUAL voltage using an

external N-channel to supply power from 5V MAIN in

S0, and an external P-Channel to provide power from 5V

Standby (5VSB) in S3.

5.

An internal LDO which regulates "3.3V Always" in S3

mode from VCC(VSB). In S3, this regulator is capable

of 1.25A peak currents with average currents limited by

the thermal design of the PCB.

At initial power-up, or when transitioning from S5, the PWM

regulator will be disabled until 5V MAIN is above its UVLO

threshold.

Table 2. ACPI States

STATE

S3#I

EN (S5#)

S3#O

SBSW

VDDQ

VTT

G1.2 LDO 3.3 ALW LDO

S5

XL

L

H

OFF

OFF

OFF

ON

S3

LH

L

L

ON

OFF

OFF

ON

S0

HH

HH

ON

ON

ON

OFF

STATE

3.3 ALW

5V Dual

S5

LDO

OFF

S3

LDO

+5VSB

S0

Q5 (MAIN)

+5 MAIN