TMP100, 101

7

SBOS231C

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OS/ALERT (OS)

The TMP100 and TMP101 feature a One-Shot Temperature

Measurement Mode. When the device is in Shutdown Mode,

writing a 1 to the OS/ALERT bit will start a single temperature

conversion. The device will return to the shutdown state at

the completion of the single conversion. This is useful to

reduce power consumption in the TMP100 and TMP101

when continuous monitoring of temperature is not required.

Reading the OS/ALERT bit will provide information about the

Comparator Mode status. The state of the POL bit will invert the

polarity of data returned from the OS/ALERT bit. For POL = 0,

the OS/ALERT will read as 0 until the temperature equals or

faults, causing the OS/ALERT bit to read as 1. The OS/ALERT

bit will continue to read as 1 until the temperature falls below

will again read as 0. The status of the TM bit does not affect the

status of the OS/ALERT bit.

HIGH AND LOW LIMIT REGISTERS

In Comparator Mode (TM = 0), the ALERT Pin of the TMP101

becomes active when the temperature equals or exceeds the

according to fault bits F1 and F0. The ALERT pin will remain

value for the same number of faults.

In Interrupt Mode (TM = 1) the ALERT Pin becomes active

secutive number of fault conditions. The ALERT pin remains

active until a read operation of any register occurs or the

device successfully responds to the SMBus Alert Response

Address. The ALERT pin will also be cleared if the device is

placed in Shutdown Mode. Once the ALERT pin is cleared,

it will only become active again by the temperature falling

ALERT pin will become active and remain active until cleared

by a read operation of any register or a successful response

to the SMBus Alert Response Address. Once the ALERT pin

is cleared, the above cycle will repeat with the ALERT pin

becoming active when the temperature equals or exceeds

device with the General Call Reset command. This will also

clear the state of the internal registers in the device returning

the device to Comparator Mode (TM = 0).

Both operational modes are represented in the Figure 4. Tables

is the same as for the Temperature Register.

used in the comparisons for the ALERT function for all con-

affect the ALERT output even if the converter is configured for

9-bit resolution.

SERIAL INTERFACE

The TMP100 and TMP101 operate only as slave devices on

the open-drain I/O lines SDA and SCL. The TMP100 and

TMP101 support the transmission protocol for fast (up to

400kHz) and high-speed (up to 3.4MHz) modes. All data

bytes are transmitted most significant bit first.

SERIAL BUS ADDRESS

To program the TMP100 and TMP101, the master must first

address slave devices via a slave address byte. The slave

address byte consists of seven address bits, and a direction

bit indicating the intent of executing a read or write operation.

The TMP100 features two address pins to allow up to eight

describes the pin logic levels used to properly connect up to eight

devices. ‘Float’ indicates the pin is left unconnected. The state of

cation and should be set prior to any activity on the interface.

Byte

D7D6D5

D4

D3D2

D1D0

1

H11

H10

H9

H8

H7

H6

H5

H4

Byte

D7D6D5

D4

D3D2

D1D0

2

H3H2H1

H0

0

0

0

0

Byte

D7D6D5

D4

D3D2

D1D0

1

L11

L10

L9

L8

L7

L6

L5

L4

Byte

D7D6D5

D4

D3D2

D1D0

2

L3L2L1

L0

0

0

0

0

ADD0

SLAVE ADDRESS

0

1001000

Float

1001001

1

1001010

TABLE XII. Address Pins and Slave Address for TMP101.

ADD1

ADD0

SLAVE ADDRESS

0

0

1001000

0

Float

1001001

0

1

1001010

1

0

1001100

1

Float

1001101

1

1

1001110

Float

0

1001011

Float

1

1001111

TABLE XI. Address Pins and Slave Addresses for TMP100.

The TMP101 features one address pin and an ALERT pin,

allowing up to three devices to be connected per bus. Pin logic

levels are described in Table XII. The address pins of the

TMP100 and TMP101 are read after reset or in response to an

the address pins is latched to minimize power dissipation

associated with detection.