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TPS65054-Q1 Datasheet(PDF) 5 Page - Texas Instruments

No. de Pieza. TPS65054-Q1
Descripción  6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT-VOLTAGE LDOs
Descarga  40 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS65054-Q1 Datasheet(HTML) 5 Page - Texas Instruments

 
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TPS65050-Q1, TPS65051-Q1, TPS65052-Q1
TPS65054-Q1, TPS65056-Q1
www.ti.com
SLVSBJ1A – SEPTEMBER 2012 – REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF, TA = –40°C to 125°C, typical values are at
TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCILLATOR
fSW
Oscillator frequency
2.025
2.25
2.475
MHz
OUTPUT
Output-voltage range for DCDC1,
VO
Externally adjustable versions
0.6
VINDCDC1/2
V
DCDC2
Vref
Reference voltage
Externally adjustable versions
600
mV
VINDCDC1/2 = 2.5 V to 6 V, 0 mA < IO = < IO(maximum)
–2%
0
2%
MODE = GND, PFM operation
DC output-voltage
DCDC1,
VO
accuracy
DCDC2(1)
VINDCDC1/2 = 2.5 V to 6 V, 0 mA < IO = < IO(maximum)
–1%
0
1%
MODE = VI, PWM operation
ΔVO
Power-save-mode ripple voltage(2)
IO = 1 mA, MODE = GND, VO = 1.3 V, bandwith = 20 MHz
25
mVPP
tStart
Start-up time
Time from active EN to start switching
170
μs
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VO
750
μs
RESET delay time
Input voltage at threshold pin rising
80
100
120
ms
PB-ONOFF debounce time
26
32
38
ms
VOL
RESET, PB_OUT output low voltage
IOL = 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V
0.2
V
IOL
RESET, PB_OUT sink current
1
mA
After PB_IN has been pulled high once; Vthreshold > 1 V and
RESET, PB_OUT output leakage current
10
nA
Vhysteresis > 1 V, VOH = 6 V
Vth
Vthreshold, Vhysteresis threshold
0.98
1
1.02
V
VLDO1, VLDO2, VLDO3 and VLDO4 Low-Dropout Regulators
Input-voltage range for LDO1, LDO2,
VI
1.5
6.5
V
LDO3, LDO4
LDO1 output-voltage range
TPS65050-Q1, TPS65052-Q1 only
1.2
3.3
LDO2 output-voltage range
TPS65050-Q1, TPS65052-Q1 only
1.8
3.3
VO
V
LDO3 output-voltage range
TPS65050-Q1, TPS65052-Q1 only
1.1
3.3
LDO4 output-voltage range
TPS65050-Q1, TPS65052-Q1 only
1.2
2.85
Feedback voltage for FB_LDO1,
V(FB)
TPS65051-Q1, TPS65054-Q1, and TPS65056-Q1 only
1
V
FB_LDO2, FB_LDO3, and FB_LDO4
Maximum output current for LDO1,
400
LDO2
IO
mA
Maximum output current for LDO3,
200
LDO4
LDO1 short-circuit current limit
VLDO1 = GND
750
LDO2 short-circuit current limit
VLDO2 = GND
850
I(SC)
mA
LDO3 and LDO4 short-circuit current
VLDO3 = GND, VLDO4 = GND
420
limit
Dropout voltage at LDO1
IO = 400 mA, VINLDO = 3.4 V
400
Dropout voltage at LDO2
IO = 400 mA, VINLDO = 1.8 V
280
mV
Dropout voltage at LDO3, LDO4
IO = 200 mA, VINLDO = 1.8 V
280
Leakage current from VinLDOx to
Ilkg
LDO enabled, VINLDO = 6.5 V, VO = 1 V at TA = 140°C
3
μA
VLDOx
Output voltage accuracy for LDO1,
VO
IO = 10 mA
–2%
1%
LDO2, LDO3, LDO4
VINLDO1,2 = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V,
Line regulation for LDO1, LDO2, LDO3,
VINLDO3,4 = VLDO3,4 + 0.5 V (minimum 2.5 V) to 6.5 V,
–1%
1%
LDO4
IO = 10 mA
Load regulation for LDO1, LDO2, LDO3,
IO = 0 mA to 400 mA for LDO1, LDO2
–1%
1%
LDO4
IO = 0 mA to 200 mA for LDO3, LDO4
Regulation time for LDO1, LDO2, LDO3,
Load change from 10% to 90%
10
μs
LDO4
PSRR
Power-supply rejection ratio
f = 10 kHz; IO = 50 mA; VI = VO + 1 V
70
dB
(1)
Output voltage specification does not include tolerance of external voltage-programming resistors.
(2)
In power-save mode, device typically enters operation at IPSM = VI / 32 Ω.
Copyright © 2012, Texas Instruments Incorporated
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